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Sat, 11 May 2024 15:04:10 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d878fsm1123875e87.206.2024.05.11.15.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 15:04:10 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:08 +0300 Subject: [PATCH v4 2/9] arm64: dts: qcom: sc8180x: correct dispcc clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240512-typec-fix-sm8250-v4-2-ad153c747a97@linaro.org> References: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 067712310560..b92b6fb73057 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3308,21 +3308,27 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sc8180x-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>, <&edp_phy 0>, - <&edp_phy 1>; + <&edp_phy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>; clock-names = "bi_tcxo", - "sleep_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk"; + "edp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SC8180X_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>;