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Tue, 28 May 2024 13:43:35 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b885sm1095493e87.127.2024.05.28.13.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 13:43:35 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 28 May 2024 23:43:19 +0300 Subject: [PATCH 01/10] dt-bindings: clock: qcom: split the non-PD schema for GCC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240528-qcom-gdscs-v1-1-03cf1b102a4f@linaro.org> References: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> In-Reply-To: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2430; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=9s74QROIdj/ssBLgC2P/yPwTNYf9hFSl4T/EYVO/gcM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVkH0ZLT9jQ32tNp7V9NTRcYxPnV9a7gJrfixM VLTecuQIOaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlZB9AAKCRCLPIo+Aiko 1fV7B/9/7Oj9mVPGNj9VASEnJSUSU37lfcviaOul0IUwCDeiNybOhCT7GxrcnaUVo3kfrvyQvVK SCzF9Ce9U0s2h6vQ6HjP9b5E+0U8+IgaZEjZE1HLkXuZOk+ZHrbj4SWmH2FYsxQTLmTPC5xM9YI XonWxUEZkEbTaILORSr1KboKMzKVMOXrq6FWyY3J5wG1H5qotkyV3hAGHPLU38hnu0qpMFFrXCn R/yZ4lxFfaczz2eLhYxG+9HVua8rXgAqtmOREwDlxV/sv6UV/w4mfsCNYK/2nh2wmGtdTmxrnvj MiUSEpKzGA+8OEpwVQzzVgMQzfV7Th7g6O9eprXZWI41ACzn X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Split no-PD version from the common qcom,gcc schema. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,gcc-nopd.yaml | 38 ++++++++++++++++++++++ .../devicetree/bindings/clock/qcom,gcc.yaml | 19 ++--------- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml new file mode 100644 index 000000000000..a941e75a930a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-nopd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Common Properties + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Common bindings for Qualcomm global clock control module providing the + clocks and resets. + +properties: + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 788825105f24..e7ec15b1780d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -14,27 +14,14 @@ description: | Common bindings for Qualcomm global clock control module providing the clocks, resets and power domains. -properties: - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 +allOf: + - $ref: qcom,gcc-nopd.yaml +properties: '#power-domain-cells': const: 1 - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - - reg - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' additionalProperties: true