diff mbox series

[v15,2/4] dt-bindings: pci: qcom: Add OPP table

Message ID 20240619-opp_support-v15-2-aa769a2173a3@quicinc.com
State Accepted
Commit bdf8e4d5d68ff78ea5c0f3f61c4f93c2305d69cf
Headers show
Series [v15,1/4] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path | expand

Commit Message

Krishna Chaitanya Chundru June 19, 2024, 3:11 p.m. UTC 
PCIe needs to choose the appropriate performance state of RPMh power
domain based on the PCIe gen speed.

Adding the Operating Performance Points table allows to adjust power
domain performance state and ICC peak bw, depending on the PCIe data
rate and link width.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
 Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Krzysztof Wilczyński June 28, 2024, 8:14 p.m. UTC | #1 
Hello,

> PCIe needs to choose the appropriate performance state of RPMh power
> domain based on the PCIe gen speed.
> 
> Adding the Operating Performance Points table allows to adjust power
> domain performance state and ICC peak bw, depending on the PCIe data
> rate and link width.

Applied to dt-bindings, thank you!

[1/1] dt-bindings: pci: qcom: Add OPP table
      https://git.kernel.org/pci/pci/c/1b029ce3b0b5

	Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
index 1496d6993ab4..d8c0afaa4b19 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
@@ -69,6 +69,10 @@  properties:
       - const: msi6
       - const: msi7
 
+  operating-points-v2: true
+  opp-table:
+    type: object
+
   resets:
     maxItems: 1