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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:35 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:30 +0200 Subject: [PATCH v5 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240709-topic-smem_speedbin-v5-2-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=1480; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qLAOTrSFtuBecm3+EwggXg43xqGrGY4RLrmT8vpNaLU=; b=felzT5CFkBH3CSD4+amuMEw8IiUfz80JoigCu+pRFOy5BlFTjJygWaDDjwtuKGHNKBhm30wZg NBUe1/jVPMZBLTAjuLJBMe6dl3+f4IGUf2f654Aut78+wx/zTfxZ3ug X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 68ba9aed5506..e3322f6aec13 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" +#include +#include + static const struct adreno_reglist a612_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1209,6 +1212,11 @@ static const struct adreno_info a7xx_gpus[] = { .gmu_chipid = 0x7020100, }, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family = ADRENO_7XX_GEN2,