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[V3,3/8] clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled

Message ID 20240731062916.2680823-4-quic_skakitap@quicinc.com
State Accepted
Commit 85e8ee59dfde1a7b847fbed0778391392cd985cb
Headers show
Series [V3,1/8] clk: qcom: clk-alpha-pll: Fix the pll post div mask | expand

Commit Message

Satya Priya Kakitapalli July 31, 2024, 6:29 a.m. UTC 
Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the
PLL is disabled. However, if the PLL is disabled then LOCK_DET will
never assert and we'll return an error. There is no reason to poll
LOCK_DET if the PLL is already disabled, so skip polling in this case.

Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 drivers/clk/qcom/clk-alpha-pll.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index eb5626095916..2ebeb277cb4d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -2136,6 +2136,9 @@  static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 
+	if (!clk_hw_is_enabled(hw))
+		return 0;
+
 	/* Wait before polling for the frequency latch */
 	udelay(5);