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[79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:38 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:12 +0200 Subject: [PATCH 2/7] drm/msm: Add submitqueue setup and close Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-2-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco , Sharat Masetty X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=2616; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=20oAYS3mWUIGbiEDLsRaCMFHZNrME6mT7hQZgI2Sra8=; b=vSb1NAIThr44gOy1adLEVkRxa/kzpiR9f4HJ/bpnUqNFI0dToOp74LyZ/El4114l5ebgPe7oT 7zYefoUGrPpA0Sj1m4eI+T3puPlPLI0vLUu2IaZ+1tO/TWm9qvPGIln X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 10 ++++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f02bb9956be..70f5c18e5aee 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -92,6 +92,10 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); + int (*submitqueue_setup)(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); + void (*submitqueue_close)(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); }; /* Additional state for iommu faults: */ @@ -522,6 +526,9 @@ struct msm_gpu_submitqueue { struct mutex lock; struct kref ref; struct drm_sched_entity *entity; + struct msm_gpu *gpu; + struct drm_gem_object *bo; + uint64_t bo_iova; }; struct msm_gpu_state_bo { diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index 0e803125a325..4ffb336d9a60 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -71,6 +71,11 @@ void msm_submitqueue_destroy(struct kref *kref) struct msm_gpu_submitqueue *queue = container_of(kref, struct msm_gpu_submitqueue, ref); + struct msm_gpu *gpu = queue->gpu; + + if (gpu && gpu->funcs->submitqueue_close) + gpu->funcs->submitqueue_close(gpu, queue); + idr_destroy(&queue->fence_idr); msm_file_private_put(queue->ctx); @@ -160,6 +165,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, { struct msm_drm_private *priv = drm->dev_private; struct msm_gpu_submitqueue *queue; + struct msm_gpu *gpu = priv->gpu; enum drm_sched_priority sched_prio; unsigned ring_nr; int ret; @@ -195,6 +201,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, queue->ctx = msm_file_private_get(ctx); queue->id = ctx->queueid++; + queue->gpu = gpu; if (id) *id = queue->id; @@ -207,6 +214,9 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, write_unlock(&ctx->queuelock); + if (gpu && gpu->funcs->submitqueue_setup) + gpu->funcs->submitqueue_setup(gpu, queue); + return 0; }