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[79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:43 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:15 +0200 Subject: [PATCH 5/7] drm/msm/A6xx: Add traces for preemption Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-5-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=2516; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=DLafHpP62zkOHtSD80kKPRoUh5A+Qyukl3VsQmH39Qc=; b=icdUKlpDMF2mVoh3JZqkgkjybL+RiUKZ0urWvjJ6sWmpBaEiMn7wHC4EkTZSN3u+1onK3gsCs +k8jqD6zTGCB/NV3x/BaC3XEyt+3NzIBzDusevWF8bGcHALiM3hTXlS X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Add trace points corresponding to preemption being triggered and being completed for latency measurement purposes. Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 7 +++++++ drivers/gpu/drm/msm/msm_gpu_trace.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c index 0d402a3bcf5a..2606835f3c6d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -7,6 +7,7 @@ #include "a6xx_gpu.h" #include "a6xx_gmu.xml.h" #include "msm_mmu.h" +#include "msm_gpu_trace.h" #define FENCE_STATUS_WRITEDROPPED0_MASK 0x1 #define FENCE_STATUS_WRITEDROPPED1_MASK 0x2 @@ -146,6 +147,8 @@ void a6xx_preempt_irq(struct msm_gpu *gpu) set_preempt_state(a6xx_gpu, PREEMPT_NONE); + trace_msm_gpu_preemption_irq(a6xx_gpu->cur_ring->id); + /* * Retrigger preemption to avoid a deadlock that might occur when preemption * is skipped due to it being already in flight when requested. @@ -262,6 +265,10 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) */ ring->skip_inline_wptr = false; + trace_msm_gpu_preemption_trigger( + a6xx_gpu->cur_ring ? a6xx_gpu->cur_ring->id : -1, + ring ? ring->id : -1); + spin_unlock_irqrestore(&ring->preempt_lock, flags); gpu_write64(gpu, diff --git a/drivers/gpu/drm/msm/msm_gpu_trace.h b/drivers/gpu/drm/msm/msm_gpu_trace.h index ac40d857bc45..7f863282db0d 100644 --- a/drivers/gpu/drm/msm/msm_gpu_trace.h +++ b/drivers/gpu/drm/msm/msm_gpu_trace.h @@ -177,6 +177,34 @@ TRACE_EVENT(msm_gpu_resume, TP_printk("%u", __entry->dummy) ); +TRACE_EVENT(msm_gpu_preemption_trigger, + TP_PROTO(int ring_id_from, int ring_id_to), + TP_ARGS(ring_id_from, ring_id_to), + TP_STRUCT__entry( + __field(int, ring_id_from) + __field(int, ring_id_to) + ), + TP_fast_assign( + __entry->ring_id_from = ring_id_from; + __entry->ring_id_to = ring_id_to; + ), + TP_printk("preempting %u -> %u", + __entry->ring_id_from, + __entry->ring_id_to) +); + +TRACE_EVENT(msm_gpu_preemption_irq, + TP_PROTO(u32 ring_id), + TP_ARGS(ring_id), + TP_STRUCT__entry( + __field(u32, ring_id) + ), + TP_fast_assign( + __entry->ring_id = ring_id; + ), + TP_printk("preempted to %u", __entry->ring_id) +); + #endif #undef TRACE_INCLUDE_PATH