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Wed, 28 Aug 2024 00:17:55 -0700 (PDT) Received: from [127.0.1.1] ([178.197.222.82]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37308200404sm14843476f8f.81.2024.08.28.00.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 00:17:55 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 28 Aug 2024 09:17:31 +0200 Subject: [PATCH 01/16] arm64: dts: qcom: ipq: change labels to lower-case Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-dts-qcom-label-v1-1-b27b72130247@linaro.org> References: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> In-Reply-To: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 ++++++------- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++++--------- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 ++++++------- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++++++------------------ 5 files changed, 61 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 7e6e2c121979..8914f2ef0bc4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -31,27 +31,27 @@ cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; }; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-size = <0x80000>; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 71328b223531..d3c3e215a15c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -31,47 +31,47 @@ cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; }; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 8edd535a188f..dbf6716bcb59 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -34,12 +34,12 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -47,12 +47,12 @@ CPU0: cpu@0 { #cooling-cells = <2>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x1>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -60,12 +60,12 @@ CPU1: cpu@1 { #cooling-cells = <2>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x2>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -73,12 +73,12 @@ CPU2: cpu@2 { #cooling-cells = <2>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x3>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -86,7 +86,7 @@ CPU3: cpu@3 { #cooling-cells = <2>; }; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -1015,10 +1015,10 @@ cpu_alert: cpu-passive { cooling-maps { map0 { trip = <&cpu_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 284a4553070f..78e1992b7495 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -32,39 +32,39 @@ cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; enable-method = "psci"; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x1>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x2>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x3>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; }; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 08a82a5cf667..130fb65a21a0 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -34,12 +34,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a73"; reg = <0x0>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -47,12 +47,12 @@ CPU0: cpu@0 { #cooling-cells = <2>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a73"; reg = <0x1>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -60,12 +60,12 @@ CPU1: cpu@1 { #cooling-cells = <2>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a73"; reg = <0x2>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -73,12 +73,12 @@ CPU2: cpu@2 { #cooling-cells = <2>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a73"; reg = <0x3>; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; @@ -86,7 +86,7 @@ CPU3: cpu@3 { #cooling-cells = <2>; }; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -863,10 +863,10 @@ cpu0_alert: cpu-passive { cooling-maps { map0 { trip = <&cpu0_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -891,10 +891,10 @@ cpu1_alert: cpu-passive { cooling-maps { map0 { trip = <&cpu1_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -919,10 +919,10 @@ cpu2_alert: cpu-passive { cooling-maps { map0 { trip = <&cpu2_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -947,10 +947,10 @@ cpu3_alert: cpu-passive { cooling-maps { map0 { trip = <&cpu3_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; };