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a=openpgp-sha256; l=980; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=gth7VehLLAYczDDqOTK1mioSLmcntX+IjHSeS1+PsRg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm3J/yK0Kr6gfauwYtKBj2YifOOoYasEb2/KJQy oQEzjAtvuWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZtyf8gAKCRCLPIo+Aiko 1eXDB/9YMK3v0BNnzKGqm5xYDSjWyN0LHPfuoGLoxqF11BB6jzZ6HjSdbB6BPi6n8/uMcF2CYCU pUhc1bXjxfVuHGaf6cHWqtrnm7QnBYbY9S7oexm20BZreHSMx1mnvyugF1faew9zNq1i2P1VmaW tewDNsm9c7RZhrMo8cO/oHOa9PCy0u9yKVQlnBYbWFEdjODYF+LEK4HQTo3Nz/eca3UAyniGYYK NoyD5wvdIVIhaTLstIx19dmx4DHhmbkyOR5XRyfpvPD6mMbJJQd3pK9+vtPWua3amdHbpfVaJaS UyTHeyQAsEcjpl2psOw4Yjpzg+Yj+fS2DFCA/EGPiMz/yeke X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Now as the arm-smmu-qcom driver gained workarounds for the A2NOC and LPASS SMMU devices, enable those two devices. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 92695375a63b..dc8bc63bdc70 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -665,8 +665,6 @@ anoc2_smmu: iommu@16c0000 { , , ; - - status = "disabled"; }; a2noc: interconnect@1704000 { @@ -1234,8 +1232,6 @@ lpass_smmu: iommu@5100000 { , , ; - - status = "disabled"; }; sram@290000 {