From patchwork Mon Sep 9 09:26:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 826680 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C41BE42A81; Mon, 9 Sep 2024 09:28:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725874100; cv=none; b=tSg0UDkffpCVELtvhAHOpQnn4xuzWtkxKHqcknwk9rjifVCF4h9kuUgXf94dVFxlv1ug5hMehzvnKuN90d6Y3BUAUAwvd1qBh/5izcsvUuljn0jZ1t+763RToKtOuOJIS2CjFLDFNiW3PdocABPxv7N+CHi5k9rslDct9j7YBgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725874100; c=relaxed/simple; bh=LmD1AK5OHpMsk2DiQe4IqObJc+ZfW7Vfm3ddiy70sk8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NedEImj2Oc2gbGT/GjHSoK/wD/Jj692ewao8tL4emWils6yisqKPEFF2uFz9iwckYMVJBGycv2+jn9YKcmc9uOFHV3owy29FyeytDedjtM0kaiBGJNl5htb5ND/QpLF31WWxVjOxjCY/L5Mw0Aj6lCnpcvDc8NSB9bHTdtYNXRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=IBCvpEsn; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IBCvpEsn" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4899Jkes016860; Mon, 9 Sep 2024 09:28:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= x8Ytd+8XfpqdKaZrwvU1etDsdzlHB0wCo04AunirNF8=; b=IBCvpEsnFXp2bRhf VIh5v93Hs+52KkQXZ/AGi9LmdysG9Y2tvc/K2Zdy3/aaddPy5Otsncvzlp2lQND5 efBWuI94AwTQ3Mj9ld+/Besmzc7PfP5usboamqBpPxcdcwiCUcJXeZT0t0Mp4dZB S4x+cCxSd649ydDyetH7BGncpKoh1+YqwZV4Z1nuTHjGbG1HNwhCcnh3LtAdnXqn DG1qJ037es1N6OVjHwso+f//wZByXD3PvEbTQTMGpvfOoCR6MSvKe9P5MzAfP07T DdqgaOiZO3fiEnVEafHPg3I0wYnYbWbkaFpiSOSBEfMTpe5EU9G2dvdbMjAuOSYF 4dieuw== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy8ntbfr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 09 Sep 2024 09:28:07 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4899S6lY010615 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Sep 2024 09:28:06 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:28:00 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 11/11] crypto: qce - Add support for lock/unlock in aead Date: Mon, 9 Sep 2024 14:56:32 +0530 Message-ID: <20240909092632.2776160-12-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HcRM-mlulboMsU700D5Rtqrp2TVIEHiF X-Proofpoint-ORIG-GUID: HcRM-mlulboMsU700D5Rtqrp2TVIEHiF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090075 Add support for lock/unlock on bam pipe in aead. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * Move qce_bam_release_lock() after qca_dma_terminate_all() api Change in [v2] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api for aead Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/aead.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 7d811728f047..13fb7af69f54 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,8 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0 && (error != -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -433,6 +435,8 @@ qce_aead_async_req_handle(struct crypto_async_request *async_req) else rctx->assoclen = req->assoclen; + qce_bam_acquire_lock(qce); + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;