From patchwork Fri Sep 13 11:55:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lijuan Gao X-Patchwork-Id: 828691 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 749B71D88A8; Fri, 13 Sep 2024 11:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726228565; cv=none; b=cRZYjodR660KHFndGiQx4k/4eo1RFdvphTxbfhfeiuVzw/KyWEAsXqH+eKwTNR7/q8Q57vByK1l2irY0Yeah17hMMfUp370wbUmaTPaj6D82LKBizhFd5O8bp4OH7O78C+6YYOKgjag9mJ17iegrl0gJC1+5iNYgomUnanc5AEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726228565; c=relaxed/simple; bh=J7RFXPVp0Pyqw/DNKpxT1uHd9AZ/lM/8Nl8rUJaU58c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gCvaGq1kGGUQ2H79pdaV4/pdLCh0pJtBLu3jufvsaW/vkP1c+B6qj4qNW4vAfz/sLwuIbOsfrINfNhsLt7ILx9QqOkW1hEfZD4sSR3asqDghtp4j+Nrqeq2/HB7vniMcxmc6hxIZn8gZeZuivDO4GqLe1jAVUyyknkGWoaHVwQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=hc6Eb4dJ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hc6Eb4dJ" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48DAWfmm025468; Fri, 13 Sep 2024 11:56:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 0W45hF7yZpC1I+dpF7s/bJ81RmiWgmp5zqtQaJQ2ZjI=; b=hc6Eb4dJuUsYAKI2 1wNSv7JPU6tbBKob9oqeukE3FjKWQHAHwB7e6ZgNhmYD6SG/hMfr3Ax6e4PQjvxy RH0EN7CCm5hvCw87NPqgJyZeXtjUcwPjeDDa6X5B+hB1HEfwCbNYsQr+VC7dFqg9 BLoIz/+4HXZlDmmFRrmPWGtgETUJ0cNQ2PcXTopkltr+kn+1urUUquGLLojhxF3f sDSX7d2Eius6Fua5kk5LmcjPaVAR1V5lYYognJJKfp9sTva9eR/Gp++HAqPVnJ4S nHWtFxUIy8k14cwtYwek0h3jOiNOIQCsbTicGQD5+0q3zweCTvlDbKtmEbYqpU55 EIfOmg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy8p8q5a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Sep 2024 11:55:59 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48DBtwo4011816 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Sep 2024 11:55:58 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Sep 2024 04:55:53 -0700 From: Lijuan Gao Date: Fri, 13 Sep 2024 19:55:28 +0800 Subject: [PATCH v2 6/6] arm64: dts: qcom: add base QCS615 RIDE dts Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240913-add_initial_support_for_qcs615-v2-6-9236223e7dab@quicinc.com> References: <20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com> In-Reply-To: <20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com> To: , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thomas Gleixner" CC: , , , Lijuan Gao X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726228536; l=1907; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=J7RFXPVp0Pyqw/DNKpxT1uHd9AZ/lM/8Nl8rUJaU58c=; b=6tvCvPKxfEt+Vc26lB4D3GTut1zAL6ELlWFL/DxUl7zCrZ4t5Sn8zg7D+aT8Dgu89bpH/fKxO aJtKI8OAIQwCK4q8s6rLABwO9OlT+rsGBtakkFLsXheE3820MDu8b13 X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IR1ZiZYIwFqezJDwxRhUHPugHTsKgO0R X-Proofpoint-ORIG-GUID: IR1ZiZYIwFqezJDwxRhUHPugHTsKgO0R X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409130083 Add initial support for Qualcomm QCS615 RIDE board and enable the QCS615 RIDE board to shell with dcc console. Signed-off-by: Lijuan Gao --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ae002c7cf126..30a1c679bbb7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts new file mode 100644 index 000000000000..761e915d4165 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "qcs615.dtsi" +/ { + model = "Qualcomm Technologies, Inc. QCS615 Ride"; + compatible = "qcom,qcs615-ride", "qcom,qcs615"; + chassis-type = "embedded"; + + chosen { + bootargs = "console=hvc0"; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; +}; + +&watchdog { + clocks = <&sleep_clk>; +};