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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-539ffff3ddfsm826195e87.149.2024.10.17.11.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 11:04:49 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 17 Oct 2024 21:04:47 +0300 Subject: [PATCH] dt-bindings: PCI: qcom,pcie-sm8550: add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241017-sar2130p-pci-v1-1-5b95e63d9624@linaro.org> X-B4-Tracking: v=1; b=H4sIAL5REWcC/x3MQQqAIBBA0avIrBN0CoyuEi1snGo2JgoRiHdPW r7F/xUKZ+ECi6qQ+ZEid+ywgwK6fDxZS+gGNDhZY50uPqMdTdKJRAcyhLiznx1DT1LmQ95/t26 tfUdn/YZeAAAA X-Change-ID: 20241017-sar2130p-pci-dc0c22bea87e To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1526; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=O15mCh3VtZU97Mpx6hgeP/jWXAjP95Snr2eA5fDon0o=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnEVG/8G68/lf7OSluZpPo++4hB+Ws2ABn0W8AS w2HBjUHOKSJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxFRvwAKCRAU23LtvoBl uDRFEACjiiUvc4JlyT2BHMwSCQBB6n2qjwJjB4kkuTTtHGHF+okKp8yzFPhmFz9ciLyRfK9PxG0 kmHEh18U6z4glv7vUbjSaT4wR8gphPEyKAHN/gpXEikXSzlsFKCrwUoghPyDrqEl4+i7yf9Aepf PxIp4xfOBzW4QdR2ClFzmPQky3yO2kNXHMO1jH4JyNA0TZk1K0TNRAXlfzND+gh50INLD4eJfMp 5AqY4nlKURTtrTIwhF0Zwp1t3rXAE94Bz2wjfBbXvwnWUxS+PXQ4K60bNcLjJ+2piuKDlcHlScH +eYTeE5Axqm0GXEmyxyOfcX/KuXwMoWl0+NNlSnt1iWhDZPkyLVcQxWI2uAwjy8stLVU8LGItR0 mABUBlaZ0ATnbP9u88hF/9WiBvXpbhzQvT6U5tzjcv8T9z35xOxzA0l71yovAg4dBX0SdSxS72Z MqCVCEdMZSYDh8TScFbynwLi9t+JR+5Af1jls04vW1p0agbKT4dMtyHp/jhFz2ypUERoh4tWJYj 1n/bLUUV3pJPrqm3HO0Rv0HaGGBiRWJryPcXZWBMUsjDCWg0Xe0dVq+Ky6+b/WX2tXnGol7qbUP MnAsIKNnKR3QLNiO7muZFaciN316JZlLBfvEByXZEJtg0a4XfyIpar8qlRlyFS10YWX9RgK49gq SIqdnb06KAadgfg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the Qualcomm SAR2130P platform the PCIe host is compatible with the DWC controller present on the SM8550 platorm, just using one additional clock. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- base-commit: 7df1e7189cecb6965ce672e820a5ec6cf499b65b change-id: 20241017-sar2130p-pci-dc0c22bea87e Best regards, diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 24cb38673581d7391f877d3af5fadd6096c8d5be..2b5498a35dcc1707e6ba7356389c33b3fcce9d0f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,sar2130p-pcie - qcom,pcie-sm8650 - const: qcom,pcie-sm8550 @@ -39,7 +40,7 @@ properties: clocks: minItems: 7 - maxItems: 8 + maxItems: 9 clock-names: minItems: 7 @@ -52,6 +53,7 @@ properties: - const: ddrss_sf_tbu # PCIe SF TBU clock - const: noc_aggr # Aggre NoC PCIe AXI clock - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + - const: qmip_pcie_ahb # QMIP PCIe AHB clock interrupts: minItems: 8