From patchwork Thu Oct 24 06:53:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 838156 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB02818A935; Thu, 24 Oct 2024 06:53:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752842; cv=none; b=dWJLcq22uIyCH7Z3nOmNIy5t4gGNP/GeIwlk1RUGi0jcO5fhkcKmnZW5sH5CgbBp174tj0nBA5oUmAkByD2bBCBvzHcCjGg3t21V7RrPRFygwpaa+YFmyM6t254omhQg1AymEFVz+n29MLqYXUbsMscZUcojJkM6D9AmJNxJGc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752842; c=relaxed/simple; bh=xBc+1L6Q/IonCQYUkezY5NPL3xHHBdmVBzv3MRLIHnU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hKzWFfTAQqYd5orSV2mXtuuEkrWLk/D+tGHonQGYtWmzFmcI8No8FBEm9LTH66ASyQtDC7uQPhSDBXZW/VrBxOi2P5cDvoFQFod+48gnB0ZPm5DsbQB5/FWmopvIztjJ22vbq1A7sON2ZqugwUgo8fZFVBOFbTC2IN0TZFYMFow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=khrS+g0O; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="khrS+g0O" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49NLXitO016171; Thu, 24 Oct 2024 06:53:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=w3QGRmNgjXIiFwwmNaUFfizy UclQYS0Fh9BYwMiMwvs=; b=khrS+g0OJXOeWylRQTXews0v5kRHXcvsn+dvlp1F /yVbZr1EQmrJm/JhV8CULLmUwZXiCH2/magEIV6JunHnHKv27qACFaJqGOF3BC7o wQzoBkM9to2DhMN6qJbM/T7Yj3kIiYg/AXwbvwfwvnXaBc4d9/n3XHPLRlwFIarm Pj8ibMCENoL7iyUPPa4L6O0V3jt25OUhQgyBdwmpZNa98MJ8xij6JVS7pPEmWorz YoFrc+8Gf61wjFAuhPOSISTxEEdS3FOZMrUiHaOyoHD/L1nBI7FP++Zy0KV7K46K yNRWmT25Yyt8/6XQjsOdsEjMK62P7OKnuwildSwqBZ+DHg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em3xmrvh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 06:53:44 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49O6rhGd030102 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 06:53:43 GMT Received: from taozha2-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 23 Oct 2024 23:53:39 -0700 From: Tao Zhang To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin CC: Tao Zhang , , , , , Subject: [PATCH v4 4/4] coresight-tpda: Optimize the function of reading element size Date: Thu, 24 Oct 2024 14:53:06 +0800 Message-ID: <20241024065306.14647-5-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241024065306.14647-1-quic_taozha@quicinc.com> References: <20241024065306.14647-1-quic_taozha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qpYHDVS8lu2-oqWH0QMbdiIp03Nm8tdF X-Proofpoint-ORIG-GUID: qpYHDVS8lu2-oqWH0QMbdiIp03Nm8tdF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 impostorscore=0 mlxscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410240052 Since the new funnel device supports multi-port output scenarios, there may be more than one TPDM connected to one TPDA. In this way, when reading the element size of the TPDM, TPDA driver needs to find the expected TPDM corresponding to the filter source. When TPDA finds a TPDM or a filter source from a input connection, it will read the Devicetree to get the expected TPDM's element size. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpda.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index ad023a2a99d1..413828f19d60 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -110,6 +110,16 @@ static int tpda_get_element_size(struct tpda_drvdata *drvdata, csdev->pdata->in_conns[i]->dest_port != inport) continue; + /* + * If this port has a hardcoded filter, use the source + * device directly. + */ + if (csdev->pdata->in_conns[i]->filter_src_fwnode) { + in = csdev->pdata->in_conns[i]->filter_src_dev; + if (!in) + continue; + } + if (coresight_device_is_tpdm(in)) { if (drvdata->dsb_esize || drvdata->cmb_esize) return -EEXIST; @@ -124,7 +134,6 @@ static int tpda_get_element_size(struct tpda_drvdata *drvdata, } } - return rc; }