| Message ID | 20241113-add-display-support-for-qcs615-platform-v2-6-2873eb6fb869@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add display support for QCS615 platform | expand |
On 2024/11/14 21:41, Dmitry Baryshkov wrote: > On Thu, 14 Nov 2024 at 15:32, Konrad Dybcio > <konrad.dybcio@oss.qualcomm.com> wrote: >> >> On 13.11.2024 12:51 PM, Fange Zhang wrote: >>> From: Li Liu <quic_lliu6@quicinc.com> >>> >>> Add support for DSI 2.3.1 (block used on QCS615). >>> Add phy configuration for QCS615 >>> >>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com> >>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> >>> --- >>> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +++++++++++++++++ >>> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++ >>> 5 files changed, 42 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c >>> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..edbe50305d6e85fb615afa41f3b0db664d2f4413 100644 >>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c >>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c >>> @@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg = { >>> }, >>> }; >>> >>> +static const struct regulator_bulk_data qcs615_dsi_regulators[] = { >>> + { .supply = "vdda", .init_load_uA = 21800 }, >>> +}; >> >> I believe refgen is also present here and you can reuse dsi_v2_4_regulators > > This was in feedback for v1... And the patch should be further split, > having DSI and PHY parts separately. ok will split the patch - DSI part drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + - DSI phy part drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++ >
On 2024/11/14 21:32, Konrad Dybcio wrote: > On 13.11.2024 12:51 PM, Fange Zhang wrote: >> From: Li Liu <quic_lliu6@quicinc.com> >> >> Add support for DSI 2.3.1 (block used on QCS615). >> Add phy configuration for QCS615 >> >> Signed-off-by: Li Liu <quic_lliu6@quicinc.com> >> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> >> --- >> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +++++++++++++++++ >> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++ >> 5 files changed, 42 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c >> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..edbe50305d6e85fb615afa41f3b0db664d2f4413 100644 >> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c >> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c >> @@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg = { >> }, >> }; >> >> +static const struct regulator_bulk_data qcs615_dsi_regulators[] = { >> + { .supply = "vdda", .init_load_uA = 21800 }, >> +}; > > I believe refgen is also present here and you can reuse dsi_v2_4_regulators yes, will fix them in next patch will remove qcs615_dsi_regulators and reuse dsi_v2_4_regulators > > Konrad
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 10ba7d153d1cfc9015f527c911c4658558f6e29e..edbe50305d6e85fb615afa41f3b0db664d2f4413 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg = { }, }; +static const struct regulator_bulk_data qcs615_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 21800 }, +}; + +static const struct msm_dsi_config qcs615_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .regulator_data = qcs615_dsi_regulators, + .num_regulators = ARRAY_SIZE(qcs615_dsi_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000 }, + }, +}; + static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { .link_clk_set_rate = dsi_link_clk_set_rate_v2, .link_clk_enable = dsi_link_clk_enable_v2, @@ -286,6 +301,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1, + &qcs615_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -23,6 +23,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001 #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000 +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001 #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index dd58bc0a49eb5ca96370f7832d9251609ac0c552..bc38fcd28e6778f5676983b78f7635ce619cd758 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_14nm_cfgs }, { .compatible = "qcom,dsi-phy-14nm-2290", .data = &dsi_phy_14nm_2290_cfgs }, + { .compatible = "qcom,dsi-phy-14nm-615", + .data = &dsi_phy_14nm_615_cfgs }, { .compatible = "qcom,dsi-phy-14nm-660", .data = &dsi_phy_14nm_660_cfgs }, { .compatible = "qcom,dsi-phy-14nm-8953", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 4953459edd636363614ecad85654614fc95cfa1d..5a2654a2e2814d21d24d0e6bd1e7811e7b537dfa 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -46,6 +46,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..42a1c76a25f54be4c8fa799994901e7fd7cfb9d9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = { { .supply = "vcca", .init_load_uA = 73400 }, }; +static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = { + { .supply = "vdda", .init_load_uA = 36000 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .has_phy_lane = true, .regulator_data = dsi_phy_14nm_17mA_regulators, @@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { .io_start = { 0x5e94400 }, .num_dsi_phy = 1, }; + +const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_14nm_36mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators), + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + .save_pll_state = dsi_14nm_pll_save_state, + .restore_pll_state = dsi_14nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xae94400 }, + .num_dsi_phy = 1, +};