From patchwork Wed Nov 13 07:23:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 842948 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC1F917B4E9; Wed, 13 Nov 2024 07:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731482660; cv=none; b=LKiOaW6z/L8urfmpbMMeb3W+bhShd5qvd32vH86pIjcELtAwxDp1nK3T2bnH1u+BFj5Wvaz1MbfTGyv51mQrx7h1rymEEq8Jp4GiasigQcd8BccjJytUJlHz0R7+BTgXRQpgGYJEToQYQV1RwKhccoX9nULPb9KEXTTiXs+4U8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731482660; c=relaxed/simple; bh=/ZnjozkXDQvnhKCuNFpJpHv2PB5U6txWdUKtNQlSc6k=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nk6zPANUoyJiPGvtRj6uqH/0vY9F9x3OkpRxadORMYYpHSzC1SR5wpQCAVxUMEEzvSLnFAE0M3igb1Cefw1cd6PqcoCn2TCEkJTKQZwttuWz2TvhwnPw6l45ui33jYCIDbQR+n3ZX3FP6LDL5/jEd7IwqwGPhvMDk8DJnUH60v0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Ezu0Sl4R; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Ezu0Sl4R" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ACMSwQE020483; Wed, 13 Nov 2024 07:24:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +VFSsKtYH6xy/ibGA9AcMWaIiDfg2L6aF9GA0bgCtfY=; b=Ezu0Sl4Rw5zZUqhE YT96LXjtp84Ad8aR/u9X3uion7USt2FUFtALfKldU3vJn4mzylv/RgQWhkwFneGx kgznad7BzurTHNueg4i0rhEZQ1+UY37xbPySGikrmQ4Y/NTWGlkbW+o9i5DQJs8s 0upMW3s0U4h/gf5fe29xaFG9Q5I2uXqG1OH5t62rsnQ/uIA/qU9prYqsuiimu7r7 2LPOBn8NgtTQ3sFTINdEUCUy4NC4nnvy7fvMK8hy1M8QwqkKas5Dc4Gh90WhA9sl 9rLTblw1SZSiMiQFeBz8qgwlIIPx1kzC8cjek4FLhddt/wQA/ZHpF8sHKEZ6WI09 daobJw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42v4kqu54r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 07:24:11 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AD7OAVd003593 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 07:24:11 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 12 Nov 2024 23:24:04 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 2/6] phy: qcom-qusb2: add QUSB2 support for IPQ5424 Date: Wed, 13 Nov 2024 12:53:12 +0530 Message-ID: <20241113072316.2829050-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241113072316.2829050-1-quic_varada@quicinc.com> References: <20241113072316.2829050-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fgi4F_kaDLy2FxwFy2CjZDsj6AdW6jsG X-Proofpoint-GUID: fgi4F_kaDLy2FxwFy2CjZDsj6AdW6jsG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130064 Add the phy init sequence for the Super Speed ports found on IPQ5424. Signed-off-by: Varadarajan Narayanan --- v2: Change uppercase hexdigits to lowercase --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index c52655a383ce..2d8fe9bc40f9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -151,6 +151,21 @@ static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), }; +static const struct qusb2_phy_init_tbl ipq5424_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x00), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc3), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), +}; + static const unsigned int ipq6018_regs_layout[] = { [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, @@ -331,6 +346,16 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = { .autoresume_en = BIT(0), }; +static const struct qusb2_phy_cfg ipq5424_phy_cfg = { + .tbl = ipq5424_init_tbl, + .tbl_num = ARRAY_SIZE(ipq5424_init_tbl), + .regs = ipq6018_regs_layout, + + .disable_ctrl = POWER_DOWN, + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(0), +}; + static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { .tbl = qusb2_v2_init_tbl, .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), @@ -905,6 +930,9 @@ static const struct phy_ops qusb2_phy_gen_ops = { static const struct of_device_id qusb2_phy_of_match_table[] = { { + .compatible = "qcom,ipq5424-qusb2-phy", + .data = &ipq5424_phy_cfg, + }, { .compatible = "qcom,ipq6018-qusb2-phy", .data = &ipq6018_phy_cfg, }, {