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Fri, 29 Nov 2024 07:59:23 GMT Received: from szioemm-lnxbld002.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 28 Nov 2024 23:59:15 -0800 From: Xiangxu Yin Date: Fri, 29 Nov 2024 15:57:46 +0800 Subject: [PATCH 6/8] drm/msm/dp: Add maximum width limitation for modes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241129-add-displayport-support-for-qcs615-platform-v1-6-09a4338d93ef@quicinc.com> References: <20241129-add-displayport-support-for-qcs615-platform-v1-0-09a4338d93ef@quicinc.com> In-Reply-To: <20241129-add-displayport-support-for-qcs615-platform-v1-0-09a4338d93ef@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I , Linus Walleij , Bartosz Golaszewski , , CC: , , , , , , , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This ensures that the modes are filtered based on hardware capabilities, specifically addressing the line buffer limitations of individual pipes. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_display.c | 3 +++ drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_panel.c | 13 +++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 4 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 4c83402fc7e0d41cb7621fa2efda043269d0a608..eb6fb76c68e505fafbec563440e9784f51e1894b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -944,6 +944,9 @@ enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); link_info = &msm_dp_display->panel->link_info; + if (mode->hdisplay > msm_dp_display->panel->max_dp_width) + return MODE_BAD; + if (drm_mode_is_420_only(&dp->connector->display_info, mode) && msm_dp_display->panel->vsc_sdp_supported) mode_pclk_khz /= 2; diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index ecbc2d92f546a346ee53adcf1b060933e4f54317..7a11f7eeb691976f06afc7aff67650397d7deb90 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -11,6 +11,7 @@ #include "disp/msm_disp_snapshot.h" #define DP_MAX_PIXEL_CLK_KHZ 675000 +#define DP_MAX_WIDTH 7680 struct msm_dp { struct drm_device *drm_dev; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 8654180aa259234bbd41f4f88c13c485f9791b1d..10501e301c5e073d8d34093b86a15d72e646a01f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -4,6 +4,7 @@ */ #include "dp_panel.h" +#include "dp_display.h" #include "dp_utils.h" #include @@ -455,6 +456,16 @@ static u32 msm_dp_panel_link_frequencies(struct device_node *of_node) return frequency; } +static u32 msm_dp_panel_max_width(struct device_node *of_node) +{ + u32 max_width = 0; + + if (of_property_read_u32(of_node, "max-width", &max_width)) + max_width = DP_MAX_WIDTH; + + return max_width; +} + static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel) { struct msm_dp_panel_private *panel; @@ -490,6 +501,8 @@ static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel) if (!msm_dp_panel->max_dp_link_rate) msm_dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2; + msm_dp_panel->max_dp_width = msm_dp_panel_max_width(of_node); + return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 7603b92c32902bd3d4485539bd6308537ff75a2c..61513644161209c243bbb623ee4ded951b2a0597 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -51,6 +51,7 @@ struct msm_dp_panel { u32 lane_map[DP_MAX_NUM_DP_LANES]; u32 max_dp_lanes; u32 max_dp_link_rate; + u32 max_dp_width; u32 max_bw_code; };