From patchwork Tue Dec 17 00:43:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 851830 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 411C81474B8; Tue, 17 Dec 2024 00:43:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734396228; cv=none; b=iO6EY29OJIS2tCziDSdp+osSukajQHgfEnnu727T/Uh4T/bXb4cDC+6euxhGCpQY9fuDsRIFn7NFkcSRfGpzHe5HaKUn/6KIAq3dNcPPRq3xm3BR6doFKYY6mxfbKY+2KhTVj486XO2kVFvLDSX2oTFCPyawPooKjpR4KSjEkxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734396228; c=relaxed/simple; bh=UR7qOV7qmwUy1ysIz80gjs3AZzlsn+f3mWzoa4vhi24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Glwz0g+4Ba8+Ismb1It9BRnUIBRO8Qmfpu37SQacgbWsqmtb62ytOCGZyGhmR/s0TKq1C7OLYt+oq59TtxBIGfFsYyFcdZ1R1pk27Uh4E9dD5DzaBnNpFVIqJODBpGNMkNJzvWmx7NopICTgIawYFO3/uHV4eZOL1VsBuWPhtAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Rm9lZWvP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Rm9lZWvP" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BGMPYgx012152; Tue, 17 Dec 2024 00:43:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= YKyfUhK1lGWDYVHUlQa6X+3g3mFnwI1+ZRPcXCWqOrA=; b=Rm9lZWvPAyztS41O rU1RipN2uX1von8cpvRxD2lt8M1CiWk+tTp3pyBT9yU21baEF6Fs1jAU/CqVEGuL lnr1XxBhHPLYbVivjYVWVm45PATJzwidR0vBYAnAtMGXkYi5Xh4k9EGaKCj8dHJw oHQuhTcRoPzBk2Oc8pFHjNnXOyYk64JwUc4YGezEQ0/tOv1SJU/PPb8vOmD5Xv9F HMqbwc4W9tCDN/2Dddu4wID9jXLYTmcuLvziN1OiI5NqgymT9HH7yEJL3dmmoGcA XFYDkxp015sKMQOflWIUg6RQrvX5RV9OVkLMYds0kyMpYLlx2aStYxxfDv3/X/Vt Furl8g== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43jw0687rq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 00:43:31 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BH0hUET028885 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 00:43:30 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 16 Dec 2024 16:43:30 -0800 From: Jessica Zhang Date: Mon, 16 Dec 2024 16:43:28 -0800 Subject: [PATCH v4 17/25] drm/msm/dpu: Fail atomic_check if CWB and CDM are enabled Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241216-concurrent-wb-v4-17-fe220297a7f0@quicinc.com> References: <20241216-concurrent-wb-v4-0-fe220297a7f0@quicinc.com> In-Reply-To: <20241216-concurrent-wb-v4-0-fe220297a7f0@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Simona Vetter , Simona Vetter CC: , , , , , Rob Clark , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-355e8 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734396205; l=1021; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=UR7qOV7qmwUy1ysIz80gjs3AZzlsn+f3mWzoa4vhi24=; b=p5hGL/dufkqvmzugx1OrGL+pQKs65A9bJ+/WQF7ZnnE2iu5TAh858BQFrRFg/bdHzxm5KU0s0 WHRrY6/rNz5AJxY9/PdT5y3qM1LmFQ6hZn5vrTaTKSIb3TXfXDJuluM X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TUmo6EteFSeKEnFk0zHbvCYn6aXX4Ulo X-Proofpoint-GUID: TUmo6EteFSeKEnFk0zHbvCYn6aXX4Ulo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170004 We cannot support both CWB and CDM simultaneously as this would require 2 CDM blocks and currently our hardware only supports 1 CDM block at most. Thus return an error if both CWB and CDM are enabled. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9bb920d28bae2706b3892c167fe2bec3fd8857f4..a6372eee916e8aba702bbefc3615d8882ddcaad9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1261,6 +1261,10 @@ static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_stat return 0; topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state); + + if (topology.cwb_enabled && topology.needs_cdm) + return -EINVAL; + ret = dpu_rm_reserve(&dpu_kms->rm, global_state, crtc, &topology); if (ret)