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Sun, 29 Dec 2024 23:08:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHWD5vLzxfrHu9wRcxilDoEnl/C3oXRCj5ziwvSSp7dnCvcIleRCk75qjbHiGfnr00af48PA== X-Received: by 2002:a05:6a20:2d11:b0:1e1:b062:f3fa with SMTP id adf61e73a8af0-1e5e080283amr49953540637.34.1735542481185; Sun, 29 Dec 2024 23:08:01 -0800 (PST) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-842aba72f44sm17131337a12.15.2024.12.29.23.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Dec 2024 23:08:00 -0800 (PST) From: Mukesh Ojha X-Google-Original-From: Mukesh Ojha To: jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Mukesh Ojha , Mukesh Ojha Subject: [PATCH] mailbox: qcom-ipcc: Reset CLEAR_ON_RECV_RD if set from boot firmware Date: Mon, 30 Dec 2024 12:36:44 +0530 Message-Id: <20241230070644.2512780-1-mojha@qti.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: C8V2M_2IfMeHF3aolk_ARc87eL_KE8Fm X-Proofpoint-ORIG-GUID: C8V2M_2IfMeHF3aolk_ARc87eL_KE8Fm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 clxscore=1011 priorityscore=1501 mlxscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412300059 From: Mukesh Ojha For some SoCs, boot firmware is using the same IPCC instance used by Linux and it has kept CLEAR_ON_RECV_RD set which basically means interrupt pending registers are cleared when RECV_ID is read and the register automatically updates to the next pending interrupt/client status based on priority. Clear the CLEAR_ON_RECV_RD if it is set from the boot firmware. Signed-off-by: Mukesh Ojha --- drivers/mailbox/qcom-ipcc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mailbox/qcom-ipcc.c b/drivers/mailbox/qcom-ipcc.c index 14c7907c6632..0b17a38ea6bf 100644 --- a/drivers/mailbox/qcom-ipcc.c +++ b/drivers/mailbox/qcom-ipcc.c @@ -14,6 +14,7 @@ #include /* IPCC Register offsets */ +#define IPCC_REG_CONFIG 0x08 #define IPCC_REG_SEND_ID 0x0c #define IPCC_REG_RECV_ID 0x10 #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14 @@ -21,6 +22,7 @@ #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c #define IPCC_REG_CLIENT_CLEAR 0x38 +#define IPCC_CLEAR_ON_RECV_RD BIT(0) #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0) #define IPCC_CLIENT_ID_MASK GENMASK(31, 16) @@ -274,6 +276,7 @@ static int qcom_ipcc_pm_resume(struct device *dev) static int qcom_ipcc_probe(struct platform_device *pdev) { struct qcom_ipcc *ipcc; + u32 config_value; static int id; char *name; int ret; @@ -288,6 +291,19 @@ static int qcom_ipcc_probe(struct platform_device *pdev) if (IS_ERR(ipcc->base)) return PTR_ERR(ipcc->base); + /* + * It is possible that boot firmware is using the same IPCC instance + * as of the HLOS and it has kept CLEAR_ON_RECV_RD set which basically + * means Interrupt pending registers are cleared when RECV_ID is read. + * The register automatically updates to the next pending interrupt/client + * status based on priority. + */ + config_value = readl(ipcc->base + IPCC_REG_CONFIG); + if (config_value & IPCC_CLEAR_ON_RECV_RD) { + config_value &= ~(IPCC_CLEAR_ON_RECV_RD); + writel(config_value, ipcc->base + IPCC_REG_CONFIG); + } + ipcc->irq = platform_get_irq(pdev, 0); if (ipcc->irq < 0) return ipcc->irq;