From patchwork Thu Jan 2 11:30:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 854764 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8CF1AC435; Thu, 2 Jan 2025 11:31:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735817488; cv=none; b=hI9lTvNnw5F9Ribkos6NapBS8rlWF4U9Vp0UjCU+vD9SWd0HZyY3myYz8DgeNDmYxbCl9LpiDDhaBvVYCQ5LjebbSHI9Xhxk3rHqIeCWfuT2JGwLv3DY/7Nv0kR5t4FSSLBG1pWbgYZwqKvUGmWRyJ6Q1dYXj7ENyFEPq4uzU1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735817488; c=relaxed/simple; bh=71FtpYofxPuRsZljt7RUB75kNyxMYW+CjPPzAy4ipkQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m/5Zj76Qyj06G3nhXwb/WO8YTfInsYdROnlPcqO5l7oh9ij22sZ4fn5fdRDj9qfqmC/kPTf50i+934MY9n9M7wc9le75npnYunJBKkB/2jYAZra6CIrpkE5DVFWLhKgBZEatF6A5wVHa8fXCyMaabqiDU5EWk4n30NgBj8flX8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=X2biQtwX; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="X2biQtwX" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5020UUIX032704; Thu, 2 Jan 2025 11:31:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wh7FHFrsbaMUmnELAnpAnab0WW9eAXgZTYTMfK9n5vM=; b=X2biQtwXa0qtM2vw zzw/6GArMDANrGwOasiDXRKbX0JJtdLoKdm8UQ54PHAVTTRs5I7YwWkte0q07Btb 9dxdZ18CSYQF3DPT+Tyyr9+foCnhGRJ5wrDk0rjF9YrWd+07JtkMZnUz2EIJRGYw Rz1R8x8wQuoDfrwgaAK8CvS7k+J6ZwhNZoasMyCShMYDOo+GgJSj9z7/bxRJdXZl svbzkP0CahOUsawU4a4Xaz4bqMRwSukiyyh1scg9UxEU7mqAha4yYXCU573XdVPd i6/e25CTxS08qxcfuzjoNPQlQpY3IW6Js4oXnzlB9GCjWCvmbyvD1Ohz7E37WvV4 Aum/rA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43wfy414kd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jan 2025 11:31:17 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 502BV8SD008627 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 2 Jan 2025 11:31:08 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 2 Jan 2025 03:31:02 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , CC: Praveenkumar I , Konrad Dybcio Subject: [PATCH v5 4/5] arm64: dts: qcom: ipq5332: Add PCIe related nodes Date: Thu, 2 Jan 2025 17:00:18 +0530 Message-ID: <20250102113019.1347068-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250102113019.1347068-1-quic_varada@quicinc.com> References: <20250102113019.1347068-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7QSysZ4lPsZVpREZV-I8YCzK2XSgg0Le X-Proofpoint-ORIG-GUID: 7QSysZ4lPsZVpREZV-I8YCzK2XSgg0Le X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501020100 From: Praveenkumar I Add phy and controller nodes for pcie0_x1 and pcie1_x2. Reviewed-by: Konrad Dybcio Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v5: Add 'num-lanes' to "pcie1_phy: phy@4b1000" Make ipq5332 as main and ipq9574 as fallback compatible Move controller nodes per address Having Konrad's Reviewed-By v4: Remove 'reset-names' as driver uses bulk APIs Remove 'clock-output-names' as driver uses bulk APIs Add missing reset for pcie1_phy Convert 'reg-names' to a vertical list Move 'msi-map' before interrupts v3: Fix compatible string for phy nodes Use ipq9574 as backup compatible instead of new compatible for ipq5332 Fix mixed case hex addresses Add "mhi" space Removed unnecessary comments and stray blank lines v2: Fix nodes' location per address --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 221 +++++++++++++++++++++++++- 1 file changed, 219 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3c3e215a15c..89daf955e4bd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -186,6 +186,43 @@ rng: rng@e3000 { clock-names = "core"; }; + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: phy@4b1000 { + compatible = "qcom,ipq5332-uniphy-pcie-phy"; + reg = <0x004b1000 0x1000>; + + clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X2_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X2PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + + num-lanes = <2>; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; @@ -212,8 +249,8 @@ gcc: clock-controller@1800000 { #interconnect-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie1_phy>, + <&pcie0_phy>, <0>; }; @@ -479,6 +516,186 @@ frame@b128000 { status = "disabled"; }; }; + + pcie1: pcie@18000000 { + compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574"; + reg = <0x00088000 0x3000>, + <0x18000000 0xf1d>, + <0x18000f20 0xa8>, + <0x18001000 0x1000>, + <0x18100000 0x1000>, + <0x0008b000 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x18200000 0x18200000 0 0x00100000>, + <0x02000000 0 0x18300000 0x18300000 0 0x07d00000>; + + msi-map = <0x0 &v2m0 0x0 0xffd>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X2_RCHG_CLK>, + <&gcc GCC_PCIE3X2_AHB_CLK>, + <&gcc GCC_PCIE3X2_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE3X2_PIPE_ARES>, + <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X2_AUX_CLK_ARES>, + <&gcc GCC_PCIE3X2_AHB_CLK_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, + <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + }; + + pcie0: pcie@20000000 { + compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574"; + reg = <0x00080000 0x3000>, + <0x20000000 0xf1d>, + <0x20000f20 0xa8>, + <0x20001000 0x1000>, + <0x20100000 0x1000>, + <0x00083000 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, + <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; + + msi-map = <0x0 &v2m0 0x0 0xffd>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X1_0_RCHG_CLK>, + <&gcc GCC_PCIE3X1_0_AHB_CLK>, + <&gcc GCC_PCIE3X1_0_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, + <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, + <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + }; }; timer {