From patchwork Thu Jan 2 11:30:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 855057 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CA4F1B0F0B; Thu, 2 Jan 2025 11:31:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735817495; cv=none; b=hmLdTIthPt+EmNq98u5P/7ahgwl8Se9yHdfBCKGWjx5SpvxD3PVh6gKcihMvvP4HnBtpDNeaLnwVuLDQWg6f2qHxUAekTsaMYIt6xp51gwpCN3X2ML2xA9uGGJ1WvHH6XLfYyjP7lq2XHeZ29DoFeBa579doUtXiAd4/7LFpRVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735817495; c=relaxed/simple; bh=HK0bcts3/EOI3z/YtbcXBJ51jSGmA7iuDWXhbO0n+lc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nNCbRlYVF/VSjQj7jRjtJOtkkgdm50q4R+DKdy/aiowTCwD5AcsWBTrv0qQuAj0uqjJihK3sdSmNfQOEOuXimKL627kWuZRAycaDye+G5Zixc8b6IYKduQFI7z/rGYMn7xvXrINMC8/ksLqsd4ZB6C4rcgjMKrObsHd+iB1+P4Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DpisShAn; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DpisShAn" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50283V5p021055; Thu, 2 Jan 2025 11:31:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hhl8LhVLSIOFxcEP2RPodjO6sTk2njoaqUrh5OIEc1k=; b=DpisShAneyngaKTw VjBPW5MTrI6n+iQSIVsYzxeAe4fRS0JPqWhBGtmpmO8nWt5SOzJTbykBJqCoFseo WZyltZkz5iNHW8zU4zfca8VYbe9sjrP0YOuHTVlM7ef5zBGlKWhU9cd6Zga6FjDf g08CEmDwvBuTobhyqF9tlHS2z4BTZZ3470G+gh66rk5fTUV31j97Dqd5vLkbBWX8 S7jEohNl72Uunt5Liy2l+VyWib3Wskutqn8W8tCYxcDBs/RnNsmelEz5ii4IIDav wwOLXiXT21ceN4Akzu6w+rH8otqhYtJ40/RYJXsff2qVZnRXXMmtF4Km25giWG0y m1RGlg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43wpy2rcs5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jan 2025 11:31:18 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 502BVFRr021610 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 2 Jan 2025 11:31:15 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 2 Jan 2025 03:31:08 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , CC: Praveenkumar I , Konrad Dybcio Subject: [PATCH v5 5/5] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Date: Thu, 2 Jan 2025 17:00:19 +0530 Message-ID: <20250102113019.1347068-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250102113019.1347068-1-quic_varada@quicinc.com> References: <20250102113019.1347068-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4hYAdnYZhUJVfEoy1Rst72AreNP5IIqj X-Proofpoint-GUID: 4hYAdnYZhUJVfEoy1Rst72AreNP5IIqj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501020100 From: Praveenkumar I Enable the PCIe controller and PHY nodes for RDP 441. Reviewed-by: Konrad Dybcio Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v5: Add 'Reviewed-by: Konrad Dybcio' v4: Fix nodes sort order Use property-n followed by property-names v3: Reorder nodes alphabetically Fix commit subject --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..79ec77cfe552 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -32,6 +32,34 @@ &sdhc { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; @@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio13";