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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223832c1bsm4261655e87.280.2025.01.03.22.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 22:19:18 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 04 Jan 2025 08:19:12 +0200 Subject: [PATCH v3 1/5] nvmem: core: fix bit offsets of more than one byte Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250104-sar2130p-nvmem-v3-1-a94e0b7de2fa@linaro.org> References: <20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org> In-Reply-To: <20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Akhil P Oommen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2179; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=DP/l7Yoeg48ucLXReCMjDDAHTnXmcOLfOXPpLm9/mx4=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBneNLgMTBJCitDFHxA6inhG5B42VbEEbUZNj++6 XYj8kLDWTGJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ3jS4AAKCRAU23LtvoBl uIo6D/9n2sALObvT7aq5loDvxyEKB1E+9JUzHPf84QwE7EUDospcOxH+mE66SauSJcpDHdkBg8P B3GZ8errhtXYeYYn+Lq8hgmyJ1f8k9Q508hLG73C8DU3n7/ebN81hbhdmeJhVAMIXcuF3NUczt9 5MeKcl7502oWP6+5zzaT2I6W2ylAM4rV4Pow6yGMWn94dxLVURxFudsxwMxt4Cz96oRhniBxXm1 q4y+WHVpPUJTwU2DMNmG2qBM2nBtApAqqhZX4JwNM4JWZASDSa2RerCTB0RZwPRX7j3JRKouHkR okOiCOJp7u6nys6oZKgYDKsTd1LJ46Oa+OIMlrlyINlLSUKiMC0TLBthoi0MIRkdsR4D2C744qT Nwe9s/9T4RM/5gM4q5yMkNz+NvGxq37a2txA5TKhookgEYn8kIMCvz/P/tj8xMKg34NFudHGeSm 25M6NZ2wJ/5LmosQx//Ch4FqyUxaxuKx3BcQ+2ZMvQcbho30ACLRgQ0/qoQQTcBEUKZ85lULuEY P4TORncL+erYKeBex1iNB37Cdjo0FjcRLJ0LvTdwm15kZi1RhQTXEwNIl5WT404VmEKGHM+8ikQ 98oTKw+8DkOcL7epaD30hqpf9o+WU6C5e2t1dTwewA0k2HgrUcp+VCVHOzLnsgogqOvFdQc1Ivt xlh8b4m1DDTj9FA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A If the NVMEM specifies a stride to access data, reading particular cell might require bit offset that is bigger than one byte. Rework NVMEM core code to support bit offsets of more than 8 bits. Signed-off-by: Dmitry Baryshkov --- drivers/nvmem/core.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index d6494dfc20a7324bde6415776dcabbb0bfdd334b..c0af43a37195c3869507a203b370615309aeee67 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -834,7 +834,9 @@ static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_nod if (addr && len == (2 * sizeof(u32))) { info.bit_offset = be32_to_cpup(addr++); info.nbits = be32_to_cpup(addr); - if (info.bit_offset >= BITS_PER_BYTE || info.nbits < 1) { + if (info.bit_offset >= BITS_PER_BYTE * info.bytes || + info.nbits < 1 || + info.bit_offset + info.nbits >= BITS_PER_BYTE * info.bytes) { dev_err(dev, "nvmem: invalid bits on %pOF\n", child); of_node_put(child); return -EINVAL; @@ -1627,21 +1629,29 @@ EXPORT_SYMBOL_GPL(nvmem_cell_put); static void nvmem_shift_read_buffer_in_place(struct nvmem_cell_entry *cell, void *buf) { u8 *p, *b; - int i, extra, bit_offset = cell->bit_offset; + int i, extra, bytes_offset; + int bit_offset = cell->bit_offset; p = b = buf; - if (bit_offset) { + + bytes_offset = bit_offset / BITS_PER_BYTE; + b += bytes_offset; + bit_offset %= BITS_PER_BYTE; + + if (bit_offset % BITS_PER_BYTE) { /* First shift */ - *b++ >>= bit_offset; + *p = *b++ >> bit_offset; /* setup rest of the bytes if any */ for (i = 1; i < cell->bytes; i++) { /* Get bits from next byte and shift them towards msb */ - *p |= *b << (BITS_PER_BYTE - bit_offset); + *p++ |= *b << (BITS_PER_BYTE - bit_offset); - p = b; - *b++ >>= bit_offset; + *p = *b++ >> bit_offset; } + } else if (p != b) { + memmove(p, b, cell->bytes - bytes_offset); + p += cell->bytes - 1; } else { /* point to the msb */ p += cell->bytes - 1;