From patchwork Fri Feb 7 07:55:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dikshita Agarwal X-Patchwork-Id: 863060 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E064F240616; Fri, 7 Feb 2025 07:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738915089; cv=none; b=tJoHGa/r3Gd6oMjvnpdMIBhAq+oIMrVgxstiLUgK/Rack7Gf+ckXMZOTFSyFwbT1FLdwmaXbJ/xSK21p0fEMtH0qNC2Iv0JoY6patYrnboQssDhKoTpXILjt5rg9fAYURUcc5RB0TD/hvX3j0ersy92sjOz095mpsndxqr43SPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738915089; c=relaxed/simple; bh=cq7TJjmOzv2SaDhUpLh2coznevHyG5NE2XaXyA1Yf5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=oIJ8TPssr62P5BrsVMs/2tzzz7boZ/p8OZlkVDCWT0oe4jQleuu2CApV0n5sf453hV1B9MD2qu25LSVp5zMOgBQV+8fCvKuWTO++ZQp2ll9VTvQwZK5h6EZ7YRZtLJtwJJZmIFIyoZbvkp1ptqJCEKX13o0pq4liEh24eTkPTOo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Tzp4n9ze; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Tzp4n9ze" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5172JJZ2004726; Fri, 7 Feb 2025 07:57:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= C8PzkfFZ9Vj20Xm1sJ0n2Ylk4FyTe+JBAkXcXmE1TpY=; b=Tzp4n9zeQgsQCRtL bMBGfQBdtVBgVgpKL/INL4CCAmXKwOyQL6Ar+D5HIKgDYVKzS9l8lwLAtae4bFWZ 8v8vwExl8HZ8waClyfbaUbQKymyvJkFYqgEv45DNZu+L8gO86r5J3s2Hej0J4pYX E3TDapaNOgyqyahAKUCOJ6UjIbRo/kVQjGZUemWBcbsIvdnX6Rju3tfUYiHJZzN9 Sn2b8+Aa7WpCl5E8yd2EVz2t5/oUPzyfunjYZR4H9Hvm2mLoP1S2XA4RLvqYNuD2 oOxE04I8gtJQZP23SnXF1UyPp+NvHTcemC/xsuwMZ70ByRdRkR2VOoSkHk9T08Y1 osOKLw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44n99e8qg0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 07:57:54 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5177vrar031447 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 07:57:53 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 23:57:46 -0800 From: Dikshita Agarwal Date: Fri, 7 Feb 2025 13:25:06 +0530 Subject: [PATCH v10 26/28] media: iris: add check to allow sub states transitions Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250207-qcom-video-iris-v10-26-ab66eeffbd20@quicinc.com> References: <20250207-qcom-video-iris-v10-0-ab66eeffbd20@quicinc.com> In-Reply-To: <20250207-qcom-video-iris-v10-0-ab66eeffbd20@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Philipp Zabel CC: Hans Verkuil , Sebastian Fricke , Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jianhua Lu , "Stefan Schmidt" , Joel Stanley , "Johan Hovold" , , , , , Dikshita Agarwal , Vedang Nagar X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738914893; l=5432; i=quic_dikshita@quicinc.com; s=20240917; h=from:subject:message-id; bh=3ouVPOI5/LfMAQdAAK/4mo4Y7vdpNLOsus75bx7hpWg=; b=KrKyKhGYFIveoypa6Z+XozmmELoyyDXVga5JPJA4Yk9F2EjtqwxlbkaYyqNuB4BTScsqaByD+ puuHmNHEMmdC8x/cx0m/WwffmhBhnMZX7DKihlqjqX9zivJ1zfN+bHk X-Developer-Key: i=quic_dikshita@quicinc.com; a=ed25519; pk=EEvKY6Ar1OI5SWf44FJ1Ebo1KuQEVbbf5UNPO+UHVhM= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KQr2Sm1jp0GvZnnlpB4td_8xj6xBz4u_ X-Proofpoint-GUID: KQr2Sm1jp0GvZnnlpB4td_8xj6xBz4u_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 phishscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070060 From: Vedang Nagar Based on the design of the state machine, add checks whether the transition from one sub-state to another is allowed. Signed-off-by: Vedang Nagar Tested-by: Stefan Schmidt # x1e80100 (Dell XPS 13 9345) Reviewed-by: Stefan Schmidt Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8550-HDK Signed-off-by: Dikshita Agarwal --- .../platform/qcom/iris/iris_hfi_gen1_command.c | 12 ++++++- drivers/media/platform/qcom/iris/iris_state.c | 40 ++++++++++++++++++++++ drivers/media/platform/qcom/iris/iris_state.h | 3 ++ 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index e1fbbb3c196d..64f887d9a17d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -135,6 +135,9 @@ static int iris_hfi_gen1_session_start(struct iris_inst *inst, u32 plane) if (!V4L2_TYPE_IS_OUTPUT(plane)) return 0; + if (inst->sub_state & IRIS_INST_SUB_LOAD_RESOURCES) + return 0; + reinit_completion(&inst->completion); iris_hfi_gen1_packet_session_cmd(inst, &packet, HFI_CMD_SESSION_LOAD_RESOURCES); @@ -153,7 +156,11 @@ static int iris_hfi_gen1_session_start(struct iris_inst *inst, u32 plane) if (ret) return ret; - return iris_wait_for_session_response(inst, false); + ret = iris_wait_for_session_response(inst, false); + if (ret) + return ret; + + return iris_inst_change_sub_state(inst, 0, IRIS_INST_SUB_LOAD_RESOURCES); } static int iris_hfi_gen1_session_stop(struct iris_inst *inst, u32 plane) @@ -180,6 +187,9 @@ static int iris_hfi_gen1_session_stop(struct iris_inst *inst, u32 plane) ret = iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); if (!ret) ret = iris_wait_for_session_response(inst, false); + + iris_inst_change_sub_state(inst, IRIS_INST_SUB_LOAD_RESOURCES, 0); + iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, VB2_BUF_STATE_ERROR); iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, diff --git a/drivers/media/platform/qcom/iris/iris_state.c b/drivers/media/platform/qcom/iris/iris_state.c index f12306e735ec..5976e926c83d 100644 --- a/drivers/media/platform/qcom/iris/iris_state.c +++ b/drivers/media/platform/qcom/iris/iris_state.c @@ -105,6 +105,43 @@ int iris_inst_state_change_streamoff(struct iris_inst *inst, u32 plane) return iris_inst_change_state(inst, new_state); } +static bool iris_inst_allow_sub_state(struct iris_inst *inst, enum iris_inst_sub_state sub_state) +{ + if (!sub_state) + return true; + + switch (inst->state) { + case IRIS_INST_INIT: + if (sub_state & IRIS_INST_SUB_LOAD_RESOURCES) + return true; + return false; + case IRIS_INST_INPUT_STREAMING: + if (sub_state & (IRIS_INST_SUB_FIRST_IPSC | IRIS_INST_SUB_DRC | + IRIS_INST_SUB_DRAIN | IRIS_INST_SUB_INPUT_PAUSE)) + return true; + return false; + case IRIS_INST_OUTPUT_STREAMING: + if (sub_state & (IRIS_INST_SUB_DRC_LAST | + IRIS_INST_SUB_DRAIN_LAST | IRIS_INST_SUB_OUTPUT_PAUSE)) + return true; + return false; + case IRIS_INST_STREAMING: + if (sub_state & (IRIS_INST_SUB_DRC | IRIS_INST_SUB_DRAIN | + IRIS_INST_SUB_DRC_LAST | IRIS_INST_SUB_DRAIN_LAST | + IRIS_INST_SUB_INPUT_PAUSE | IRIS_INST_SUB_OUTPUT_PAUSE)) + return true; + return false; + case IRIS_INST_DEINIT: + if (sub_state & (IRIS_INST_SUB_DRC | IRIS_INST_SUB_DRAIN | + IRIS_INST_SUB_DRC_LAST | IRIS_INST_SUB_DRAIN_LAST | + IRIS_INST_SUB_INPUT_PAUSE | IRIS_INST_SUB_OUTPUT_PAUSE)) + return true; + return false; + default: + return false; + } +} + int iris_inst_change_sub_state(struct iris_inst *inst, enum iris_inst_sub_state clear_sub_state, enum iris_inst_sub_state set_sub_state) @@ -124,6 +161,9 @@ int iris_inst_change_sub_state(struct iris_inst *inst, prev_sub_state = inst->sub_state; + if (!iris_inst_allow_sub_state(inst, set_sub_state)) + return -EINVAL; + inst->sub_state |= set_sub_state; inst->sub_state &= ~clear_sub_state; diff --git a/drivers/media/platform/qcom/iris/iris_state.h b/drivers/media/platform/qcom/iris/iris_state.h index a5c0cad4a78c..78c61aac5e7e 100644 --- a/drivers/media/platform/qcom/iris/iris_state.h +++ b/drivers/media/platform/qcom/iris/iris_state.h @@ -113,6 +113,8 @@ enum iris_inst_state { * @IRIS_INST_SUB_OUTPUT_PAUSE: last buffer is received form firmware as part * of drc sequence. This indicates that * firmware is paused to process any further output frames. + * @IRIS_INST_SUB_LOAD_RESOURCES: indicates all the resources have been loaded by the + * firmware and it is ready for processing. */ enum iris_inst_sub_state { IRIS_INST_SUB_FIRST_IPSC = BIT(0), @@ -122,6 +124,7 @@ enum iris_inst_sub_state { IRIS_INST_SUB_DRAIN_LAST = BIT(4), IRIS_INST_SUB_INPUT_PAUSE = BIT(5), IRIS_INST_SUB_OUTPUT_PAUSE = BIT(6), + IRIS_INST_SUB_LOAD_RESOURCES = BIT(7), }; int iris_inst_change_state(struct iris_inst *inst,