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Wed, 12 Feb 2025 07:15:53 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 11 Feb 2025 23:15:47 -0800 From: Yongxing Mou Date: Wed, 12 Feb 2025 15:12:25 +0800 Subject: [PATCH 2/4] dt-bindings: display/msm: Add stream 1 pixel clock for QCS8300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250212-mst_qcs8300-v1-2-38a8aa08394b@quicinc.com> References: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> In-Reply-To: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , "Bjorn Andersson" , Konrad Dybcio CC: , , , , , Yongxing Mou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Yongxing Mou --- .../devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml index eb7f36387f748793ebf662baded4a13a61b3ce39..610742ceebf8ee5e140a409bfeb92d9f43085214 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -53,7 +53,6 @@ patternProperties: compatible: items: - const: qcom,qcs8300-dp - - const: qcom,sm8650-dp required: - compatible @@ -164,7 +163,7 @@ examples: }; displayport-controller@af54000 { - compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp"; + compatible = "qcom,qcs8300-dp"; pinctrl-0 = <&dp_hot_plug_det>; pinctrl-names = "default"; @@ -181,15 +180,18 @@ examples: <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>, <&mdss_edp_phy 1>; phys = <&mdss_edp_phy>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>;