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Thu, 20 Feb 2025 02:08:17 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b3305sm15304645a91.6.2025.02.20.02.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 02:08:16 -0800 (PST) From: Jun Nie Date: Thu, 20 Feb 2025 18:07:52 +0800 Subject: [PATCH v2 1/5] drm/msm/dsi: add support VBIF_CTRL_PRIORITY to v2.8.0 controller Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250220-dual-dsi-v2-1-6c0038d5a2ef@linaro.org> References: <20250220-dual-dsi-v2-0-6c0038d5a2ef@linaro.org> In-Reply-To: <20250220-dual-dsi-v2-0-6c0038d5a2ef@linaro.org> To: Rob Clark , Abhinav Kumar , Jessica Zhang , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jun Nie , Jonathan Marek X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740046076; l=1578; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=lyKLAJr554JAOHjjCnxBQz5CBxEAxvVfUFObcdY1ag4=; b=m9wZrPVBSR+QFJ2DUz/SNoHz3xMrc85nVdPM1VuwlkkM2KmcuqsZt4IzPpcd3vqZEPukV8UFz Q1wZLZvkNnCDMVDPFv4QVErnUTSQ+9VvDwTKh1lvQQdWOSoY1Qs3jj7 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= This change originates from the Qualcomm Android Linux driver. It is essential to support a dual-DSI configuration with two panels in some circumstances per testing. As the name suggests, this modification may enhance the bandwidth robustness of a bus. Co-developed-by: Jonathan Marek Signed-off-by: Jonathan Marek Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 42e100a8adca09d7b55afce0e2553e76d898744f..f59c4cd6bc8cdb31c1302f8e3ff395486c0b4898 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2238,13 +2238,23 @@ int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, return ret; } +#define DSI_VBIF_CTRL (0x01CC - 4) +#define DSI_VBIF_CTRL_PRIORITY 0x07 + void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, u32 len) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; + u32 reg; dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); dsi_write(msm_host, REG_DSI_DMA_LEN, len); + if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_8_0) { + reg = dsi_read(msm_host, DSI_VBIF_CTRL); + reg |= (DSI_VBIF_CTRL_PRIORITY & 0x7); + dsi_write(msm_host, DSI_VBIF_CTRL, reg); + } dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); /* Make sure trigger happens */