| Message ID | 20250227-topic-sm8650-pmu-ppi-partition-v3-1-0f6feeefe50f@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/3] arm64: dts: qcom: sm8650: fix PMU interrupt flag | expand |
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index de960bcaf3ccf6e2be47bf63a02effbfb75241bf..895f70cf6f57a84dda38604789d5ad6d80471944 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1417,17 +1417,17 @@ opp-3302400000 { pmu-a520 { compatible = "arm,cortex-a520-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; pmu-a720 { compatible = "arm,cortex-a720-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; pmu-x4 { compatible = "arm,cortex-x4-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; psci {
The ARM PMU interrupt is sometimes defined as IRQ_TYPE_LEVEL_LOW, or IRQ_TYPE_LEVEL_HIGH, but downstream and recent platforms used the IRQ_TYPE_LEVEL_HIGH flag so align the SM8650 definition to have a functional PMU working. Fixes: c8a346e408cb ("arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs") Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)