From patchwork Mon Mar 3 12:43:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viken Dadhaniya X-Patchwork-Id: 869888 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0852F20FA8F; Mon, 3 Mar 2025 12:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741005852; cv=none; b=aCJoOXxCSZjKBOq6Vfpus6qJlfxD+hWqfIddZ197D5Bul8AivfwMSsFryyDfCzAEc2M3ZiC9/Brpms7M9HdwABoVz8niWcJK+Pt6AcJqWvVdiJUl/CgJ2YUmpvgDIYmv0MPCwV0jdxu2aoRIMuhytpGqI0jonNKonBNvl/az8lw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741005852; c=relaxed/simple; bh=PHeduBcIpzCKBNRSvqbcT2mhpdYPXVDtpDzdG7i9fV4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fAyGg8wyqmy+Oc1E8K4iB1VKQzQ06VK349YVnxK9KFn6IVHjiOxB5taVgdiupnt2SfdOF2MTQ8jm85tkGFR1kI1zP77tFi1C1hXQBfMvb2zu06qfgJWNk0w99ac2G2r5K4mg2HV7rrU9BXDMMbjSMz0Q70sY0Ms2OuOtsc6I+Sw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YgPMMVwO; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YgPMMVwO" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 523AGFVE029520; Mon, 3 Mar 2025 12:44:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=nYpHBtSYRyt a+cExHBEdShbQ2o/vafExiYTWwEm5fxg=; b=YgPMMVwOmg6hvNl88xf1Uu/YC09 rwJ+J1Eu1U191svtsfN57UeyfLhuEEVsz2D/ZyTfJGmNDelhAc69RHReHrS+LlzU UiGfjAq/9jjkwGZPgGq++CiBgpuhPitMp7Vr1IBT0eBu/jC2efDQPUCiYRO+tKVW 78d5NnvrDkWF8IjcWGmsb3Qmi+d+xSh1RLFefEfjBFGt16Lfbj3PizQ130gvAJ7C a6M2DPdGSLL+Y+3GkUcErjJr124Z3lVS9Vrs63cpenkgQnIcbS3wJLGFWH9G1ZvI y9GTngKkY8xkzR/lwDSBSVP4tiM8c+w9KSqnPlIv7eYoKSqvZtqFMaHxkUA== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 453tm5mxag-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Mar 2025 12:44:06 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 523Ci3bZ015210; Mon, 3 Mar 2025 12:44:03 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 453uakx55w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Mar 2025 12:44:03 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 523Ci3ON015200; Mon, 3 Mar 2025 12:44:03 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com ([10.213.97.252]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 523Ci2cu015196 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Mar 2025 12:44:03 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 4047106) id 3956D53B; Mon, 3 Mar 2025 18:14:02 +0530 (+0530) From: Viken Dadhaniya To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, broonie@kernel.or, andersson@kernel.org, konradybcio@kernel.org, johan+linaro@kernel.org, dianders@chromium.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org Cc: quic_msavaliy@quicinc.com, quic_anupkulk@quicinc.com, Viken Dadhaniya Subject: [PATCH v3 2/9] dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Date: Mon, 3 Mar 2025 18:13:42 +0530 Message-Id: <20250303124349.3474185-3-quic_vdadhani@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303124349.3474185-1-quic_vdadhani@quicinc.com> References: <20250303124349.3474185-1-quic_vdadhani@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rMrATk6ErGjVoPcL6cp5NTYHwmXhIXwO X-Proofpoint-GUID: rMrATk6ErGjVoPcL6cp5NTYHwmXhIXwO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-03_07,2025-03-03_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 adultscore=0 clxscore=1015 bulkscore=0 mlxscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503030098 Introduce a new YAML schema for QUP-supported peripherals. Define common properties used across QUP-supported peripherals. Add property `qcom,gsi-dma-allowed` to configure the Serial Engine (SE) for QCOM GPI DMA mode. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- .../soc/qcom/qcom,se-common-props.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml new file mode 100644 index 000000000000..a111e51bb1c4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,se-common-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QUP Peripheral-specific properties for I2C, SPI and SERIAL bus. + +description: + The Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) is + a programmable module that supports a wide range of serial interfaces + such as UART, SPI, I2C, I3C, etc. This defines the common properties used + across QUP-supported peripherals. + +maintainers: + - Mukesh Kumar Savaliya + - Viken Dadhaniya + +properties: + qcom,gsi-dma-allowed: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the Serial Engine (SE) to transfer data in QCOM GPI DMA mode. + By default, FIFO mode (PIO/CPU DMA) will be selected. + +additionalProperties: true