From patchwork Tue Mar 11 19:02:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 872530 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 605E52676EB for ; Tue, 11 Mar 2025 19:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741719782; cv=none; b=DiwrOs+G/MPZQHbCwf7K+piPYSnot1I/CXoa7dfZ4KI5DWYUkzcUSeey2Pbq5gMPdcPxK8RhB/rTl/YrnMkRh+5bunca7uQWLpmo895nf8UhqlU/TykXyJ3+9Q1O4mNbUS1lvWaoXSFSvZ6rqfjjrHpSdh0+oAxZDD+nMhyfN0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741719782; c=relaxed/simple; bh=UcKkS3k0jvSD/ddvvevhlsuwSmEdXbmmiDyEA0164wE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=un+P9OlWQVpyJOiVyU9m5ChkTckGZjdNn/RrJvt0ruffwddRbD6PZdlhkbVL6212agtqLh213WTJa5esN+joyXG9LDdKes35FNkLO4QMeABn8oiPm9qvK5Z/g1kvumwz1QrhJLf18ZWavExlS7MoByTg7ffzJ3kIFCCKnMfwnMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=DuHJBTJm; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="DuHJBTJm" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-391295490c8so351802f8f.3 for ; Tue, 11 Mar 2025 12:03:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741719779; x=1742324579; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=C+hRVJbIr8TPiCBY2fZdOw7v3FZEOYNL1tXsuzKYPNM=; b=DuHJBTJmDTLbWpuSZ8f3p4qyhON/E4M6YF4pxkoPOBmRf0pxO2KEbSLFzeGNsXuANs AuYTpxGq1OTQdg9cbX3EQH4M8fYdD4PPfAruzlv6G8CrBK7DulT0bG472wkGZ8vZKLm7 W8QuG5D1NG4N+j9tUkTWXhcvgzgUKZd4veuv2Zwx/l4Xg/utq5V6HfbApQTsi1hBg6Hs jg7rUVsYPZe9vsSjd2fDNP6PjaIAsbTnS8HwlsgtWw6pQuuWwrlIY/t+pD4LVVKvalyA eSsxeQwgDfrWkJ72nTZ48x8DlyQWBaI+IiZHZsZ4quukRXjew9FsUxdenBSLMWfUOjzd fT/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741719779; x=1742324579; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C+hRVJbIr8TPiCBY2fZdOw7v3FZEOYNL1tXsuzKYPNM=; b=dSQtKL9Zv4i0PXETqzuUKcSHMbtaJ0R1nUPTpiBeNrpIhoUHwcixz4wae8BnNzUBK1 lvhsV0bzzpit2QjMw4icGO2GjA3FqLa7h+YqFr2eQzdrRMQ/6xCO4L16hgEwfoSGFlqh 8omzZYDicYgGfYFP8BFCzM5+5HVTiFJbJgnBmfG06kzFTeFiGg9xxEUXcT4rIf3+Q5b6 BS6l+ZvFCbk8TgJBxkbMDbcEimLfbqmh5JoWeMJFQBsIYLATPGsDohwLYh2qXS2E2F75 HxwMx9AN2sP8MhJ86vXisxGUKOgy+rf/q8XA3YpbGxSCtLIrT4ki1oj2tAvgddOrbAEx Fx/A== X-Gm-Message-State: AOJu0YwbdMRP7HqLzUCIjROTzQjgTN7zUa0OIp6vSuThZkzOxreBVP7c 4HSpYcsXDpnfi3glDWAhptJzmvRxTS/SZIbXjJmQBa6uXVoZmQ+44Nh0Q37nyHvvkfv3m7zERiP G X-Gm-Gg: ASbGncvHBt8rzd7KdldaLgjl7RfH8WLFOfA3obTJh4Fiqf2KQeIKN78v5C1H2HM43zd jFgTecf4mnAdk+n3IgxqTR0kReK1/n5GKSvc3cs55EH0dM1w+ssHrEi8pphgmNrTlGkh64wknKM /EIOAc+NpYUh1erMY0reVZ1m0Zu5In8Ul3hu6LkTTrTuyps2ghodHqyLOTgUDINcOuVtR5QfMl4 g2wudRy9PsFMNInbd79gGweRZdJ3Vn/ExtBkBGAFDIt6U7tPjOkhJ9wOvAr1D7PoCBOdfb0wxmB EoJLUX6gyhXOHfmthrT1D97FTpgGdYTatK81xk9aIoDPgiF+iNeYJyjIjbiEkwGHlqCfnQ== X-Google-Smtp-Source: AGHT+IEkWpg1HaeDpZaYYUXbUvhlQ/Q197STG+56q4hfvBeFJYVihpapfAvsoij3kVZySLWxB6HaDA== X-Received: by 2002:a05:600c:1992:b0:439:9b3f:2dd9 with SMTP id 5b1f17b1804b1-43d01c305cfmr25919725e9.7.1741719778714; Tue, 11 Mar 2025 12:02:58 -0700 (PDT) Received: from [127.0.1.1] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce70d13b4sm127681155e9.38.2025.03.11.12.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 12:02:58 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:02:06 +0100 Subject: [PATCH v4 16/19] drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-b4-sm8750-display-v4-16-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7581; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=UcKkS3k0jvSD/ddvvevhlsuwSmEdXbmmiDyEA0164wE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBn0IizMrGmQ3fBIyUnEoidCzxF4Lu69NZ+BMWxH So3ippAHDGJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ9CIswAKCRDBN2bmhouD 1wPyD/sFIt/IFNTiwrzXycWl+SgUzHR9Lt+OtkLz76XBSUPh46Px1JUnqg/YwnIo+ObT+zCiep/ Z+AbpRsu64r42NiETP+TVlo7s/cQ+KSB7qX7iVQfF47VdvDgkIGkjuHWfCozduefbz8TdkzA+7e wvDAH2WI6BFrsrMz52NWeyBStWP2vVQQahorOUfnl88hpsQLWTU+4SW3dsKWpi5Ax15ctL6zd60 I7rNE2bXXubZI+sLpKSxs6SqwN9+wAoLwDfOTmNjdfm3VEWrbmTru7yLOwtfO990AKqJMfgy7P8 ykFmWl2omK0gk8d2yVYrd4/Zhzc0XbgrNGn08oJqmaa+MJryCvv39sz5uTpZCqCS6CIlzOaZF1q qMseZTx96pQRnx21wkxwCUV4Ms9oOA5rZ/Ph2ldWNi6ltSGLwvC16bPOWID4iLGFvMEAY428pKa 7OOwdkOvTbnpzSAY6v4Rib1GkW/pk+knIauRWgynNXv+2cL1PaM9m+OIDXCtVL4bXW5abWK1Aw0 0yaYHN21hfym8eTwGfhVpUPd0LMuRLLL5TYgHEP+Y57W2UGvWjkehC2T1Ey0s/VzH6ipFf5lDDc OCYTSOVOCLKMvObShD8NTobFnXlgFQqep0GJCT/7nfSyehgHoVXY7injpXifVigAGEbfANdVjUB VQJAQT5+jhs/RpQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register differences and new implementations of setup_alpha_out, setup_border_color and so one for this. Signed-off-by: Krzysztof Kozlowski --- Changes in v4: 1. Lowercase hex, use spaces for define indentation 2. _dpu_crtc_setup_blend_cfg(): pass mdss_ver instead of ctl Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 19 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++++-- 2 files changed, 94 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index a4b0fe0d9899b32141928f0b6a16503a49b3c27a..90f47fc15ee5708795701d78a1380f4ab01c1427 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -320,14 +320,20 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, } static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, - struct dpu_plane_state *pstate, const struct msm_format *format) + struct dpu_plane_state *pstate, + const struct msm_format *format, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_mixer *lm = mixer->hw_lm; uint32_t blend_op; - uint32_t fg_alpha, bg_alpha; + uint32_t fg_alpha, bg_alpha, max_alpha; fg_alpha = pstate->base.alpha >> 8; - bg_alpha = 0xff - fg_alpha; + if (mdss_ver->core_major_ver < 12) + max_alpha = 0xff; + else + max_alpha = 0x3ff; + bg_alpha = max_alpha - fg_alpha; /* default to opaque blending */ if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha != 0xff) { + if (fg_alpha != max_alpha) { bg_alpha = fg_alpha; blend_op |= DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, /* coverage blending */ blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha != 0xff) { + if (fg_alpha != max_alpha) { bg_alpha = fg_alpha; blend_op |= DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | @@ -482,7 +488,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format, + ctl->mdss_ver); if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode = 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..f220a68e138cb9e7c88194e53e47391de7ed04f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -19,12 +19,20 @@ /* These register are offset to mixer base + stage base */ #define LM_BLEND0_OP 0x00 + +/* = v12 DPU */ +#define LM_BORDER_COLOR_0_V12 0x1c +#define LM_BORDER_COLOR_1_V12 0x20 + +/* >= v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_CONST_ALPHA_V12 0x08 #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 @@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, } } +static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx, + struct dpu_mdss_color *color, + u8 border_en) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + + if (border_en) { + DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12, + (color->color_0 & 0x3ff) | + ((color->color_1 & 0x3ff) << 16)); + DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12, + (color->color_2 & 0x3ff) | + ((color->color_3 & 0x3ff) << 16)); + } +} + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) { dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); @@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } +static void +dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, + u32 stage, u32 fg_alpha, + u32 bg_alpha, u32 blend_op) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + int stage_off; + u32 const_alpha; + + if (stage == DPU_STAGE_BASE) + return; + + stage_off = _stage_offset(ctx, stage); + if (WARN_ON(stage_off < 0)) + return; + + const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); +} + static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { @@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } +static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx, + uint32_t mixer_op_mode) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + int op_mode, stages, stage_off, i; + + stages = ctx->cap->sblk->maxblendstages; + if (stages <= 0) + return; + + for (i = DPU_STAGE_0; i <= stages; i++) { + stage_off = _stage_offset(ctx, i); + if (WARN_ON(stage_off < 0)) + return; + + /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */ + op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off); + if (mixer_op_mode & BIT(i)) + op_mode |= BIT(30); + else + op_mode &= ~BIT(30); + + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode); + } +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, c->idx = cfg->id; c->cap = cfg; c->ops.setup_mixer_out = dpu_hw_lm_setup_out; - if (mdss_ver->core_major_ver >= 4) + if (mdss_ver->core_major_ver >= 12) + c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12; + else if (mdss_ver->core_major_ver >= 4) c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha; else c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config; - c->ops.setup_alpha_out = dpu_hw_lm_setup_color3; - c->ops.setup_border_color = dpu_hw_lm_setup_border_color; + if (mdss_ver->core_major_ver < 12) { + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3; + c->ops.setup_border_color = dpu_hw_lm_setup_border_color; + } else { + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12; + c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12; + } c->ops.setup_misr = dpu_hw_lm_setup_misr; c->ops.collect_misr = dpu_hw_lm_collect_misr;