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Tue, 22 Apr 2025 08:13:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH29UjTy52gEf1iD1SG2ZzoQEhDY0WDrzGQUF8zZOI7EJJmV4LK4GbJX0iN2LNLzDWhsaYNHA== X-Received: by 2002:a05:6830:6806:b0:72a:1821:aa9c with SMTP id 46e09a7af769-73006211596mr12334379a34.8.1745334796654; Tue, 22 Apr 2025 08:13:16 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.qualcomm.com ([2a01:e0a:82c:5f0:10e3:ecaa:2fb2:d23a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa433303sm15403950f8f.24.2025.04.22.08.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 08:13:16 -0700 (PDT) From: Loic Poulain To: lumag@kernel.org, quic_abhinavk@quicinc.com, robdclark@gmail.com Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH] drm/msm/dsi: Fix 14nm DSI PHY PLL Lock issue Date: Tue, 22 Apr 2025 17:13:14 +0200 Message-Id: <20250422151314.173561-1-loic.poulain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: BUtKeroC3-ja0gtEP3Vpf3JEA63KiO0Q X-Proofpoint-GUID: BUtKeroC3-ja0gtEP3Vpf3JEA63KiO0Q X-Authority-Analysis: v=2.4 cv=IP8CChvG c=1 sm=1 tr=0 ts=6807b20e cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=xqWC_Br6kY4A:10 a=XR8D0OoHHMoA:10 a=QcRrIoSkKhIA:10 a=EUspDBNiAAAA:8 a=jcYjSkQ04VlNN69X9EcA:9 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_07,2025-04-22_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 mlxscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504220115 To configure and enable the DSI PHY PLL clocks, the MDSS AHB clock must be active for MMIO operations. This is typically handled during the DSI PHY enabling process. However, since these PLL clocks are registered as proper entities within the clock framework, they can be enabled apart from the DSI PHY, leading to enabling failures (and subsequent warnings): ``` msm_dsi_phy 5e94400.phy: [drm:dsi_pll_14nm_vco_prepare] *ERROR* DSI PLL lock failed ------------[ cut here ]------------ dsi0pllbyte already disabled WARNING: CPU: 3 PID: 1 at drivers/clk/clk.c:1194 clk_core_disable+0xa4/0xac CPU: 3 UID: 0 PID: 1 Comm: swapper/0 Tainted: Tainted: [W]=WARN Hardware name: Qualcomm Technologies, Inc. Robotics RB1 (DT) pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [...] ``` This issue is particularly prevalent at boot time during the disabling of unused clock (clk_disable_unused()) which includes enabling the parent clock(s) when CLK_OPS_PARENT_ENABLE flag is set. This problem is often mitigated via clk_ignore_unused kernel param... To fix this issue properly, we take a clk reference from the clk_prepare callback and release it in clk_unprepare. Signed-off-by: Loic Poulain --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 3a1c8ece6657..7a547ae8e749 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -543,6 +543,8 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) if (unlikely(pll_14nm->phy->pll_on)) return 0; + clk_prepare_enable(pll_14nm->phy->ahb_clk); + if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); @@ -554,6 +556,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) if (unlikely(!locked)) { DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n"); + clk_disable_unprepare(pll_14nm->phy->ahb_clk); return -EINVAL; } @@ -576,6 +579,8 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); pll_14nm->phy->pll_on = false; + + clk_disable_unprepare(pll_14nm->phy->ahb_clk); } static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,