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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25a9a308sm3868948b3a.136.2025.04.25.16.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 16:48:07 -0700 (PDT) From: Unnathi Chalicheemala Date: Fri, 25 Apr 2025 16:48:01 -0700 Subject: [PATCH v6 1/3] firmware: qcom_scm: Add API to get waitqueue IRQ info Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250425-multi_waitq_scm-v6-1-cba8ca5a6d03@oss.qualcomm.com> References: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> In-Reply-To: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Prasad Sodagudi , Satya Durga Srinivasu Prabhala , Trilok Soni , Bartosz Golaszewski , Unnathi Chalicheemala X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745624885; l=4335; i=unnathi.chalicheemala@oss.qualcomm.com; s=20240514; h=from:subject:message-id; bh=HwSmczY1BPfAzd6mqaQZTmW0WxFuAC6Q6eQmyL2FVcg=; b=uDBkoWIyiXlYh0Cny/rX2dEV+G7u6bEMULbDg3HWxfc5BNFsYGmpNODZ8wpdviHmeNUdCLEj/ IXbMilpSbdRBhR8zZJng++qWgGrvusNCJ30TkEe4tS0zSgsGNVmWm9T X-Developer-Key: i=unnathi.chalicheemala@oss.qualcomm.com; a=ed25519; pk=o+hVng49r5k2Gc/f9xiwzvR3y1q4kwLOASwo+cFowXI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDE3MiBTYWx0ZWRfX899wdmxlQIrl 9uLjbe7tcmd1dEjH7gIHBVJc0189BvkquukMAfBTPzYk5tmeXbufzHlet1YBSkKGfR+CBfDGvoM WYV2dR0tYfkCAdzD0dsaFxQX/k/vqD0SjhfMMnBanTf7EE+gg7un+Bh9iUyJquBxYGybs5avPIp g2+v7qI3Yk4eG7oRMcp0fnxeokbZNWvW3YWFsVq5+XWqNGw5gC0kSnUnGn/6ES7/bYahx7vdtjN KYR1hNZl/byrYdvK7BIVfSlMalR656F28BpsnGayyjbN+J8Hq6WV/UK/IdWSPIybAvdCJ/yVGCH o9Oqweezzza8R/qj9J/wWeGg8Gdkdlv28rXxUGjeV0SPhIiCDuQ5biZ/d3hzkwno8G2M24Llidy 41gSCBjzZn7EKtTElDoKVTs+PPh1wEb8HVXFZ+mv353YeqQ1X9caVlOG1cXFW1QsmWU5u3Om X-Proofpoint-GUID: JKTHXMzAEoZGp3zQ69Ka_vEiwo0S07Zo X-Proofpoint-ORIG-GUID: JKTHXMzAEoZGp3zQ69Ka_vEiwo0S07Zo X-Authority-Analysis: v=2.4 cv=M5VNKzws c=1 sm=1 tr=0 ts=680c1f3a cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=BWC7kBQSOfkspHPoMaoA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_07,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250172 Bootloader and firmware for SM8650 and older chipsets expect node name as "qcom_scm", in order to patch the wait queue IRQ information. However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly defined fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 60 +++++++++++++++++++++++++++++++++++++++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index fc4d67e4c4a67efc77e0135c06db47bc14d0aeaa..529e1d067b1901c4417a1f1fd9c3255ee31de532 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -29,12 +29,18 @@ #include #include #include +#include #include "qcom_scm.h" #include "qcom_tzmem.h" static u32 download_mode; +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -2094,6 +2100,55 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 virq) +{ + if (virq >= GIC_SPI_BASE && virq <= GIC_MAX_SPI) { + fwspec->param[0] = GIC_SPI; + fwspec->param[1] = virq - GIC_SPI_BASE; + } else if (virq >= GIC_ESPI_BASE && virq <= GIC_MAX_ESPI) { + fwspec->param[0] = GIC_ESPI; + fwspec->param[1] = virq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected virq: %d\n", virq); + return -ENXIO; + } + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; + fwspec->param_count = 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(void) +{ + int ret; + u32 hwirq; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_WAITQ, + .cmd = QCOM_SCM_WAITQ_GET_INFO, + .owner = ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + struct irq_fwspec fwspec; + struct device_node *parent_irq_node; + + ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + + hwirq = res.result[1] & GENMASK(15, 0); + + ret = qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + parent_irq_node = of_irq_find_parent(__scm->dev->of_node); + + fwspec.fwnode = of_node_to_fwnode(parent_irq_node); + + ret = irq_create_fwspec_mapping(&fwspec); + + return ret; +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -2250,7 +2305,10 @@ static int qcom_scm_probe(struct platform_device *pdev) /* Paired with smp_load_acquire() in qcom_scm_is_available(). */ smp_store_release(&__scm, scm); - irq = platform_get_irq_optional(pdev, 0); + irq = qcom_scm_get_waitq_irq(); + if (irq < 0) + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0) { if (irq != -ENXIO) { ret = irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 097369d38b84efbce5d672c4f36cc87373aac24b..7c6cb3154b394ab910bf7775a5ae07a28e0b57a5 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -148,6 +148,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01