| Message ID | 20250425-sm6350-gdsc-val-v1-1-1f252d9c5e4e@fairphone.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/4] clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs | expand |
On 4/25/2025 5:42 PM, Luca Weiss wrote: > Compared to the msm-4.19 driver the mainline GDSC driver always sets the > bits for en_rest, en_few & clk_dis, and if those values are not set > per-GDSC in the respective driver then the default value from the GDSC > driver is used. The downstream driver only conditionally sets > clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. > > Correct this situation by explicitly setting those values. For all GDSCs > the reset value of those bits are used. > > Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350") > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > drivers/clk/qcom/camcc-sm6350.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c > index 1871970fb046d7ad6f5b6bfcce9f8ae10b3f2e93..8aac97d29ce3ff0d12e7d09fe65fd51a5cb43c87 100644 > --- a/drivers/clk/qcom/camcc-sm6350.c > +++ b/drivers/clk/qcom/camcc-sm6350.c > @@ -1695,6 +1695,9 @@ static struct clk_branch camcc_sys_tmr_clk = { > > static struct gdsc bps_gdsc = { > .gdscr = 0x6004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "bps_gdsc", > }, > @@ -1704,6 +1707,9 @@ static struct gdsc bps_gdsc = { > > static struct gdsc ipe_0_gdsc = { > .gdscr = 0x7004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "ipe_0_gdsc", > }, > @@ -1713,6 +1719,9 @@ static struct gdsc ipe_0_gdsc = { > > static struct gdsc ife_0_gdsc = { > .gdscr = 0x9004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "ife_0_gdsc", > }, > @@ -1721,6 +1730,9 @@ static struct gdsc ife_0_gdsc = { > > static struct gdsc ife_1_gdsc = { > .gdscr = 0xa004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "ife_1_gdsc", > }, > @@ -1729,6 +1741,9 @@ static struct gdsc ife_1_gdsc = { > > static struct gdsc ife_2_gdsc = { > .gdscr = 0xb004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "ife_2_gdsc", > }, > @@ -1737,6 +1752,9 @@ static struct gdsc ife_2_gdsc = { > > static struct gdsc titan_top_gdsc = { > .gdscr = 0x14004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "titan_top_gdsc", > }, > Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c index 1871970fb046d7ad6f5b6bfcce9f8ae10b3f2e93..8aac97d29ce3ff0d12e7d09fe65fd51a5cb43c87 100644 --- a/drivers/clk/qcom/camcc-sm6350.c +++ b/drivers/clk/qcom/camcc-sm6350.c @@ -1695,6 +1695,9 @@ static struct clk_branch camcc_sys_tmr_clk = { static struct gdsc bps_gdsc = { .gdscr = 0x6004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "bps_gdsc", }, @@ -1704,6 +1707,9 @@ static struct gdsc bps_gdsc = { static struct gdsc ipe_0_gdsc = { .gdscr = 0x7004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ipe_0_gdsc", }, @@ -1713,6 +1719,9 @@ static struct gdsc ipe_0_gdsc = { static struct gdsc ife_0_gdsc = { .gdscr = 0x9004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ife_0_gdsc", }, @@ -1721,6 +1730,9 @@ static struct gdsc ife_0_gdsc = { static struct gdsc ife_1_gdsc = { .gdscr = 0xa004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ife_1_gdsc", }, @@ -1729,6 +1741,9 @@ static struct gdsc ife_1_gdsc = { static struct gdsc ife_2_gdsc = { .gdscr = 0xb004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ife_2_gdsc", }, @@ -1737,6 +1752,9 @@ static struct gdsc ife_2_gdsc = { static struct gdsc titan_top_gdsc = { .gdscr = 0x14004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "titan_top_gdsc", },
Compared to the msm-4.19 driver the mainline GDSC driver always sets the bits for en_rest, en_few & clk_dis, and if those values are not set per-GDSC in the respective driver then the default value from the GDSC driver is used. The downstream driver only conditionally sets clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. Correct this situation by explicitly setting those values. For all GDSCs the reset value of those bits are used. Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- drivers/clk/qcom/camcc-sm6350.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)