| Message ID | 20250430-b4-sm8750-display-v5-6-8cab30c3e4df@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm: Add support for SM8750 | expand |
On Wed, Apr 30, 2025 at 03:00:36PM +0200, Krzysztof Kozlowski wrote: > On SM8750 the setting rate of pixel and byte clocks, while the parent > DSI PHY PLL, fails with: > > disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration. > > DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in > CMN_CTRL_0 asserted. > > Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is > enabled during rate changes. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Patch is independent and can go via separate tree. Including here for > complete picture of clock debugging issues. > > Changes in v5: > 1. New patch > --- > drivers/clk/qcom/dispcc-sm8750.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c > index 877b40d50e6ff5501df16edcffb6cf3322c65977..d86f3def6dd06b6f6f7a25018a856dcc86fc48eb 100644 > --- a/drivers/clk/qcom/dispcc-sm8750.c > +++ b/drivers/clk/qcom/dispcc-sm8750.c > @@ -393,7 +393,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { > .name = "disp_cc_mdss_byte0_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > - .flags = CLK_SET_RATE_PARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, > .ops = &clk_byte2_ops, > }, > }; > @@ -712,7 +712,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { > .name = "disp_cc_mdss_pclk0_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > - .flags = CLK_SET_RATE_PARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, I assume that these flags should be set for DSI1 clocks too. > .ops = &clk_pixel_ops, > }, > }; > > -- > 2.45.2 >
On 03/05/2025 00:42, Dmitry Baryshkov wrote: > On Wed, Apr 30, 2025 at 03:00:36PM +0200, Krzysztof Kozlowski wrote: >> On SM8750 the setting rate of pixel and byte clocks, while the parent >> DSI PHY PLL, fails with: >> >> disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration. >> >> DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in >> CMN_CTRL_0 asserted. >> >> Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is >> enabled during rate changes. >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> --- >> >> Patch is independent and can go via separate tree. Including here for >> complete picture of clock debugging issues. >> >> Changes in v5: >> 1. New patch >> --- >> drivers/clk/qcom/dispcc-sm8750.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c >> index 877b40d50e6ff5501df16edcffb6cf3322c65977..d86f3def6dd06b6f6f7a25018a856dcc86fc48eb 100644 >> --- a/drivers/clk/qcom/dispcc-sm8750.c >> +++ b/drivers/clk/qcom/dispcc-sm8750.c >> @@ -393,7 +393,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { >> .name = "disp_cc_mdss_byte0_clk_src", >> .parent_data = disp_cc_parent_data_1, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), >> - .flags = CLK_SET_RATE_PARENT, >> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, >> .ops = &clk_byte2_ops, >> }, >> }; >> @@ -712,7 +712,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { >> .name = "disp_cc_mdss_pclk0_clk_src", >> .parent_data = disp_cc_parent_data_1, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), >> - .flags = CLK_SET_RATE_PARENT, >> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, > > I assume that these flags should be set for DSI1 clocks too. Indeed. Best regards, Krzysztof
diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c index 877b40d50e6ff5501df16edcffb6cf3322c65977..d86f3def6dd06b6f6f7a25018a856dcc86fc48eb 100644 --- a/drivers/clk/qcom/dispcc-sm8750.c +++ b/drivers/clk/qcom/dispcc-sm8750.c @@ -393,7 +393,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops = &clk_byte2_ops, }, }; @@ -712,7 +712,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops = &clk_pixel_ops, }, };
On SM8750 the setting rate of pixel and byte clocks, while the parent DSI PHY PLL, fails with: disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration. DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in CMN_CTRL_0 asserted. Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is enabled during rate changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Patch is independent and can go via separate tree. Including here for complete picture of clock debugging issues. Changes in v5: 1. New patch --- drivers/clk/qcom/dispcc-sm8750.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)