From patchwork Tue May 6 05:43:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 888280 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F9C62957BE; Tue, 6 May 2025 05:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=Cvs65TYkBrazaLbrYSCkUowim2b6KC8JJ8lycd2ejzElt7PCl7GeGx5Qqn+3gbKwBJgHQeqg34n9Fcx3584MwLe4NtKV+tku1cDrdl5PYyr0lP7Fuqm6BcAHeExMXgq6Vz5a9IMvRZu9/Yx+SULCnWWp7coedE4KpArh1RXQADM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; c=relaxed/simple; bh=Dy3wXknrid1H8icen2dOkX/4GKSFoZJYyCsyt5p20QI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GaPCgDSbVUNdaR6UrY/ntcHCVZq/h1rA46GS1/tVswksRPIm7bwDM+fRjs6PcOvfVo7wKIfxwf1oleNAMBAMMAAd0ad4Ad9nER0dOSi3NEMOtntLsdh7CL4/xqMSRkbc+MYh4I9NIAZEtE0TvKkH6MEFVQpJk0PTzBmRMR1q+Zk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d/iNOyjL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d/iNOyjL" Received: by smtp.kernel.org (Postfix) with ESMTPS id E8FDDC4CEFA; Tue, 6 May 2025 05:44:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746510261; bh=Dy3wXknrid1H8icen2dOkX/4GKSFoZJYyCsyt5p20QI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=d/iNOyjLHuPyqmau5W8AgcRTUTMT8ux6llAQyM76asC2YzRMdHPi33aCOgQFgQRWs 4MNBVOOntRcmgQG1Jt7Y2dM6kH5oWLFVzYHfRBfMfIMJn4Fvm9WKJ8sYp5XRFsSzE4 zm+sXiJw7zHhWwLA0DHl4lCAXCe/Jmq8f0mxedET2qS/TbFwcpzKdyZC8jW5KL8yDA Bc4KqC2LcCv8gks4b3BpOKdowGP6kfZ620lsPbamhiVtfG2/T2aHajXoUJilIfUC/w syWpfwaAVHZJ9rfmnSnawjkGz4OCw8g27n54waADOGZBLLgRhwOdfVfQGpR3qnTqTb DA5LtA+B9Tjog== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3AB3C3ABBE; Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:37 +0400 Subject: [PATCH v2 5/6] arm64: dts: ipq5018: Add CMN PLL node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-5-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=2485; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=JG4puk3te0VbG/hCbL1JZAa8YmHtOXbXdjPdx67V0/s=; b=J1Ipn55wgYH4TRNvLfZdY4tP1ymeKf01XpzCsQD0N82+tgRrJlPDP9M01afPFBgredMUfhpWU 4wbBnTXgsmNAc57eGQPY9zvfcbj+VgEsDwDGsNEbXaUzuQ9oukoWFP2 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 8914f2ef0bc47fda243b19174f77ce73fc10757d..6992d164fa965c760ce2738307f6e103d3ff3a20 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ #include -#include #include +#include +#include #include / { @@ -16,6 +17,14 @@ / { #size-cells = <2>; clocks { + ref_96mhz_clk: ref-96mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -25,6 +34,12 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; cpus { @@ -147,6 +162,20 @@ usbphy0: phy@5b000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5018-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names = "ref", + "ahb", + "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <9600000000>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>;