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Tue, 6 May 2025 11:19:08 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 6 May 2025 04:19:04 -0700 From: Jyothi Kumar Seerapu To: Vinod Koul , Mukesh Kumar Savaliya , Viken Dadhaniya , Andi Shyti , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= CC: , , , , , , , Subject: [PATCH v6 1/2] dmaengine: qcom: gpi: Add GPI Block event interrupt support Date: Tue, 6 May 2025 16:48:43 +0530 Message-ID: <20250506111844.1726-2-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250506111844.1726-1-quic_jseerapu@quicinc.com> References: <20250506111844.1726-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=dYmA3WXe c=1 sm=1 tr=0 ts=6819f02d cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=NISQXaMT3V-eHe_uHBIA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: LsbNNL4t4SJ4u437EngkHGJo5ABxZVS4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA2MDEwOCBTYWx0ZWRfXxduG0wT/Tiqj BYUaMbD1Ma7y2dQax0FLdxmi0XmunAl820iuBI7xTHCowqdS8zVjTIUCwwamGWJiMsExq60A3x3 U4tM4oR8kZ5PKoso3RVrg0oxH2ceBA+1Uzw8MEOY4d5hocyOXaXO2rK7Poy9ddH7PEOcnfW3Aiq Y8jR8zNpF81pVSv9eusYKVvH5YeXuRkE6+Dp2PQteDhqKTywa3SUdD+Vq27GCerjBkWi7vO2a3N QcxrTdSFab9I8J4sVq5r0SOJ7PkaEhjCL7NvaR0qDpWLrSu8t2OG+lh+mfT3a4sHHmic+xw+H80 JCCqafi8jI9x+lFSq0Wmuvor7C/x8Chka2PHGsikTfp15xtK5Y42meIic8uvuKAp0OdA//T0HAG atKYhfX1A+TUNXuhsygHPRJ+G4NgHek0b6BjC/rC/8Nw3Z/k/Jnsdiwf01Yt1uNNx9w/HdGF X-Proofpoint-GUID: LsbNNL4t4SJ4u437EngkHGJo5ABxZVS4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-06_05,2025-05-05_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1011 adultscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505060108 GSI hardware generates an interrupt for each transfer completion. For multiple messages within a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism. Enabling BEI instructs the GSI hardware to prevent interrupt generation and BEI is disabled when an interrupt is necessary. When using BEI, consider splitting a single multi-message transfer into chunks of 8 messages internally and so interrupts are not expected for the first 7 message completions, only the last message triggers an interrupt, indicating the completion of 8 messages. This BEI mechanism enhances overall transfer efficiency. Signed-off-by: Jyothi Kumar Seerapu --- v5 ->v6: - For updating the block event interrupt bit, instead of relying on bei_flag, decision check is moved with DMA_PREP_INTERRUPT flag. v4 -> v5: - BEI flag naming changed from flags to bei_flag. - QCOM_GPI_BLOCK_EVENT_IRQ macro is removed from qcom-gpi-dma.h file, and Block event interrupt support is checked with bei_flag. v3 -> v4: - API's added for Block event interrupt with multi descriptor support for I2C is moved from qcom-gpi-dma.h file to I2C geni qcom driver file. - gpi_multi_xfer_timeout_handler function is moved from GPI driver to I2C driver. v2-> v3: - Renamed gpi_multi_desc_process to gpi_multi_xfer_timeout_handler - MIN_NUM_OF_MSGS_MULTI_DESC changed from 4 to 2 - Added documentation for newly added changes in "qcom-gpi-dma.h" file - Updated commit description. v1 -> v2: - Changed dma_addr type from array of pointers to array. - To support BEI functionality with the TRE size of 64 defined in GPI driver, updated QCOM_GPI_MAX_NUM_MSGS to 16 and NUM_MSGS_PER_IRQ to 4. drivers/dma/qcom/gpi.c | 3 +++ include/linux/dma/qcom-gpi-dma.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index b1f0001cc99c..7e511f54166a 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1695,6 +1695,9 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); + + if (!(i2c->dma_flags & DMA_PREP_INTERRUPT)) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_BEI); } for (i = 0; i < tre_idx; i++) diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 6680dd1a43c6..ebac0d3edff2 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -65,6 +65,7 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @dma_flags: Flags indicating DMA capabilities */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +79,7 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + unsigned int dma_flags; }; #endif /* QCOM_GPI_DMA_H */