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Thu, 8 May 2025 06:21:23 GMT Received: from hu-pbrahma-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 7 May 2025 23:21:20 -0700 From: Pratyush Brahma Date: Thu, 8 May 2025 11:51:02 +0530 Subject: [PATCH v3] arm64: dts: qcom: qcs8300: add the pcie smmu node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250508-qcs8300-pcie-smmu-v3-1-c6b4453b0b22@quicinc.com> X-B4-Tracking: v=1; b=H4sIAE5NHGgC/33NTQ6CMBCG4auQrq1pp0WKK+9hXOA4yCz4a6XRE O5uYWNMjMv3S+aZWQTyTEEcs1l4ihy471KYXSawqbo7Sb6lFqAgV6AOcsTgjFJyQCYZ2naSFp0 GjYUpyYl0N3iq+bmZ50vqhsOj96/tRdTr+k+LWmrpiEiRyV1+xdM4MXKHe+xbsXoRPoaF8pcBy bA2B+eq2lBVfBvLsrwBg+H1rPgAAAA= X-Change-ID: 20250206-qcs8300-pcie-smmu-4c8121c739e8 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Dmitry Baryshkov , "Pratyush Brahma" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Pratyush Brahma --- Changes in v3: - Revised interrupt numbers and global-interrupts to v1 after rechecking as Konrad suggested. - Added Dmitry's R-by tag based on v1 - Link to v2: https://lore.kernel.org/r/20250429-qcs8300-pcie-smmu-v2-1-445288af3ea7@quicinc.com Changes in v2: - Updated the global-interrupts and interrupts based on Konrad's suggestions - Link to v1: https://lore.kernel.org/r/20250206-qcs8300-pcie-smmu-v1-1-8eee0e3585bc@quicinc.com --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) --- base-commit: a13f6e0f405ed0d3bcfd37c692c7d7fa3c052154 change-id: 20250206-qcs8300-pcie-smmu-4c8121c739e8 Best regards, diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..fe88244771583de9fed7b7e88c69a14872d4ffc8 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -3199,6 +3199,81 @@ apps_smmu: iommu@15000000 { ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>,