From patchwork Thu May 8 18:12:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888858 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D69B12882DA; Thu, 8 May 2025 18:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728024; cv=none; b=YI2SRDWAmOb2nUq5NuJbM4ZeFTEnqeoCX55lCVYTC1/tH91ddSNMmlMhEXaT6V2lb5hUtfWOelx9n5DiL31oQ0/NrkELpufmbR4yW3QE+UAF+TCS8HiAUQ2TQNEwV25FziuzeXSOIGiirsf/nfGtQBmMJNzvPdsJ0Mn7+FRmuuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728024; c=relaxed/simple; bh=L1yDHV1hA6bvULOD3ci6a6151CWiuV5UXbptlJcu4kg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jpUzihf9rkOYEp5HcYsi5biZnoZb5CJw59s8NOPTJFsAXk2j/C1JwlSHAxUrHtvAdjv/9QcshwLdeMwlorwbwIyvM8fE/Je7aMjzbme96jUKsk52cIcKr0qVrLXcrP3MgW7AG45cQNsXJ1vRSIkoKwyHWEbDA47vt7qS0JivHo0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lAbVtyma; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lAbVtyma" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 640AFC4CEEB; Thu, 8 May 2025 18:13:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728024; bh=L1yDHV1hA6bvULOD3ci6a6151CWiuV5UXbptlJcu4kg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lAbVtymavHqsYzezQ/0PbugXh+0TQmsyfNb0sxem0j3JX8G5b99uJ5VutdtnWzepN XTQ5/lMW5vJeBAt0L4y14256WJTkhHAwvGThvPFjPzxU0KR3SKZKwaxqKJtZURZptR iXgQqMSkOwKgat0H+6MxtXAbXrAlrfv0U/7wILPnQDM4JLvdubseWW4RAw1NzXOu4T p2SFEkGY2HcUjMcUvpuE0Sg+tYBgZYyMO4LEjiRQ8mm1E5Xw7lXw35TYB6SYeXxKn3 xLnQ42IFzO0JROB2KcAObcbTjd82tO4ICwE2Q16E7HbOuTTvmMlh/ZJggRrTCpKrGU TgG48Iv5PAloQ== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:36 +0200 Subject: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-4-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=3470; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=p4HE/DWs11+jjamEyvelb/+uaNoHp2f4kQN5BS4HGmw=; b=aMqKFG1K1L+L3nDLtzCEAH8+8E5RFXdLoDea6EOjlq0HhkWbAHSk5MmddV9WP2mmphz2n4er8 cmxsyvERgTWAY/cm6cfJq68qCBMDoXdOcfJKVGJY4IQN1arHJV0x1m4 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Start the great despaghettification by getting a pointer to the common UBWC configuration, which houses e.g. UBWC versions that we need to make decisions. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); } -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { + /* Inherit the common config and make some necessary fixups */ + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(gpu->common_ubwc_cfg)) + return -EINVAL; + gpu->ubwc_config.rgb565_predicator = 0; gpu->ubwc_config.uavflagprd_inv = 0; gpu->ubwc_config.min_acc_len = 0; @@ -663,6 +668,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.highest_bank_bit = 1; gpu->ubwc_config.min_acc_len = 1; } + + return 0; } static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -2540,7 +2547,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); - a6xx_calc_ubwc_config(adreno_gpu); + ret = a6xx_calc_ubwc_config(adreno_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + /* Set up the preemption specific bits and pieces for each ringbuffer */ a6xx_preempt_init(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 2348ffb35f7eb73a26da47881901d9111dca1ad9..b7f7eb8dcb272394dce8ed1e68310a394c1734a9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1149,6 +1149,12 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev, + sizeof(*adreno_gpu->common_ubwc_cfg), + GFP_KERNEL); + if (!adreno_gpu->common_ubwc_cfg) + return -ENOMEM; + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); if (!gpu_name) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a8f4bf416e64fadbd1c61c991db13d539581e324..06be95d3efaee94e4107a484ad3132e0a6a9ea46 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -12,6 +12,8 @@ #include #include +#include + #include "msm_gpu.h" #include "adreno_common.xml.h" @@ -243,6 +245,7 @@ struct adreno_gpu { */ u32 macrotile_mode; } ubwc_config; + const struct qcom_ubwc_cfg_data *common_ubwc_cfg; /* * Register offsets are different between some GPUs.