From patchwork Thu May 8 18:12:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888857 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 806B1286D60; Thu, 8 May 2025 18:13:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728034; cv=none; b=oXSX+KtzCgA6woiIOuc9Ggv1KyFwe2xM/YRT+F5LldCHH/OSmWOaQY66daYUskfceSDyNXkDU4LH+HeZm7I8DPJ+Qc2XWtdBzBv3BsfLONEMTw/ttgTUpZuBIyoVpquZBgMaEprLdXR8g86pzWKv2bWgFEiCSDXTfCeXtTJpqmg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728034; c=relaxed/simple; bh=Lv2H2E4AyyMQYzCZzyIEsB3d9G7LQVe4hPuS8/c3LpI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i1qtOQCDaI0JN8v2FBD7EugK317imF2cc3hAjTKW0erG72e8TIAfkkgl8OQ5v7uCtbf1BqdMkhycIxRYr696cBwBcJgl2BUQTIBdaH9GRramJPHm2Z4KayLIeyXG6XUqiwOqakRAwZiX0+MTeCDUR1oGf2LZsRshSqeesF0BYHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dFHAmHWL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dFHAmHWL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4500C4CEEB; Thu, 8 May 2025 18:13:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728033; bh=Lv2H2E4AyyMQYzCZzyIEsB3d9G7LQVe4hPuS8/c3LpI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dFHAmHWLwAlUiyDGkmCAMkvLk1tF7BGeJ7NLrw8U4VJDzAbQ1vBhqk+JXi1CVFjJB yKJZax6ovjrq1Gwng9U5+5V3IuQdKR44FgnjJLk5owVKIhFSOBYQYIDcrB3pQxWfcU LtecXwy5W+pKdQViuTVkkXvCCPwTQGeffWKYnIV3t33vOYXTKXiDaf05fJrX4Bybn1 7j47TetX94z+9D0H++FFJks+BPvO7KWkJqoEOS0VVA1QPzkhNRoHmE/6o14J60BoPP 6pIE5/5Ad81ho1hnPdogbWRoEmaE82K5+QA1lTLtgza0D9QppaOUtUfXtw+S3hzS53 W4m9v3G8xnEQQ== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:38 +0200 Subject: [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-6-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=2928; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=3SEvTkNZ3L/kNlWcW+k5wOJurVA/HyPxiQtQjhnYwpA=; b=qqviDPJMFQPwKe71QA81ljC4ITfUnxo6ggEkhj/WyqTX3DrnWowALnn8UGZtFl538Y6lNDb0v duHQPtRPjGTA8donlyMaH6m3t+IZo6wHEl43cNGBU0YbIz9vpdfMaSp X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Instead of setting it on a gpu-per-gpu basis, converge it to the intended "is A650 family or A7xx". Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5fe0e8e72930320282a856e1ff77994865360854..e1eab0906b6c460528da82a94a285ef181e0b479 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -593,7 +593,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) return -EINVAL; gpu->ubwc_config.rgb565_predicator = 0; - gpu->ubwc_config.uavflagprd_inv = 0; gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; @@ -615,15 +614,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit = 0; - if (adreno_is_a621(gpu)) { + if (adreno_is_a621(gpu)) gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.uavflagprd_inv = 2; - } if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit = 3; gpu->ubwc_config.rgb565_predicator = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } @@ -638,21 +634,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 3; gpu->ubwc_config.rgb565_predicator = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; gpu->ubwc_config.rgb565_predicator = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; gpu->ubwc_config.ubwc_swizzle = 0x4; } if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit = 1; - gpu->ubwc_config.uavflagprd_inv = 2; gpu->ubwc_config.macrotile_mode = 1; } @@ -667,6 +660,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; @@ -689,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | - adreno_gpu->ubwc_config.uavflagprd_inv << 4 | + uavflagprd_inv << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);