From patchwork Thu May 8 18:12:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 888616 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5501A286D75; Thu, 8 May 2025 18:14:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728047; cv=none; b=C/rGvyN4ANxT5NlNyLpF9m6Umvh9CPwWXAHU4OQ0g4BFhFQwBshkIkCpL2Dc6xkacFYmjygVlzon0qg2wmhR63NpPDwP0ZbD3g374gTRqvo28PnW55FVo7vdvcow7NkjgKCYULnuxzUv0J5skPkVYuwLcn06gxlH/Yst6tWJJMI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746728047; c=relaxed/simple; bh=pNIxZjZ2B/51L9q0LkjHEJ+VOHIF4Sj29Z/AUMN2ll4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gJoULA1GdXUVhbkSDuMJDc9wjDW9qG8yNgRWHf8Hlt4Kw7G70S719vmnoqIUix2Hj2P+O474jnMSwgu6UVqvGoJkSubDi7R81zLVg0f6JTdUN5+M1YoifDu0BHBZxYiGIZTs0JX20PDKLNfbYWyEL+D6rMV8kEMXhBYO8pS58Og= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uv55DTsk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uv55DTsk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E679AC4CEEE; Thu, 8 May 2025 18:14:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746728047; bh=pNIxZjZ2B/51L9q0LkjHEJ+VOHIF4Sj29Z/AUMN2ll4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uv55DTskdWSXkLNuDEp1V0My46NKrg32Ke5lxPC1fH4cwnFUtLq12MPsryhaQoqCb gkvGMPJ0QNw0vUUN6I0qR/87fJ8sAVPbFZM77Ley1Nhf/no9iITmc7o1O1Hw2ecxjR Fpuyf0ZXQkDarzpmJPRNQpWtnrFneWuAZ2kK16upKiNFdwkLmEhgDZOQUCigevtGAH nuYxccp9O3V+aU5DTQwd7I5sh3kLAmoeS1iS+8HEqO5M32zFVVcBGBmUzqeSQY99T0 LQEjNceI4lg1p+/KiVaFufnALVmG/8k6S2xi8RhDnmkU0S7AI+ZnkXUhe4MFbeuFSU OimTFqmBPi6aA== From: Konrad Dybcio Date: Thu, 08 May 2025 20:12:41 +0200 Subject: [PATCH RFT 09/14] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250508-topic-ubwc_central-v1-9-035c4c5cbe50@oss.qualcomm.com> References: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> In-Reply-To: <20250508-topic-ubwc_central-v1-0-035c4c5cbe50@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746728002; l=2523; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=z6lGwAxT1SUsyRprEZFFJcrrC3aZdUlc0NVcPu988ts=; b=vmW2Q0ybkgGBJ2RY8AMRpaem1hMRWkeSRx7Zkm9uRGpOK+Eo6NwFmUQMqF1j9zDEAwG77ib7f 5dCOLPwt6LMComgCvBDMenWtN33jIuBvgNemkdxejiYoLZ0jD47SXfN X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's supposed to be on when the UBWC encoder version is >= 4.0. Drop the per-GPU assignments. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index afe4fa8e9325988af37ff12adb61faae66d746ba..60f89a2d851a5c383fc14cce4c483f630132a9a6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -592,7 +592,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (IS_ERR(gpu->common_ubwc_cfg)) return -EINVAL; - gpu->ubwc_config.rgb565_predicator = 0; gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; @@ -619,7 +618,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; } @@ -633,13 +631,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 3; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 0; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; gpu->ubwc_config.ubwc_swizzle = 0x4; } @@ -662,6 +658,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0; const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg; + bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit; bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0; @@ -671,7 +668,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | - adreno_gpu->ubwc_config.rgb565_predicator << 11 | + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);