| Message ID | 20250508081514.3227956-6-quic_wenbyao@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: x1e80100-qcp: Add power supply and sideband signals for PCIe RC | expand |
On Thu, May 08, 2025 at 04:15:14PM +0800, Wenbin Yao wrote: > From: Qiang Yu <quic_qianyu@quicinc.com> > > All PCIe PHYs on the X1E80100 SOC require the vdda-qref, which feeds QREF > clocks provided by the TCSR device. This still looks wrong and you never replied to why these supplies shouldn't be handled by the tcsr clock driver that supplies these clocks: https://lore.kernel.org/lkml/aBHUmXx6N72_sCH9@hovoldconsulting.com/ > Hence, restore the vdda-qref request for the 6th PCIe instance by reverting > commit 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref > supplies"). For the 4th PCIe instance (Gen3 x2), add a new driver data > entry, namely x1e80100_qmp_gen3x2_pciephy_cfg, which is a copy of > sm8550_qmp_gen3x2_pciephy_cfg but uses sm8550_qmp_phy_vreg_l instead. > > Fixes: 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") > Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") > Cc: Johan Hovold <johan+linaro@kernel.org> > Cc: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Johan
On Thu, May 08, 2025 at 04:50:30PM +0800, Qiang Yu wrote: > > On 5/8/2025 4:20 PM, Johan Hovold wrote: > > On Thu, May 08, 2025 at 04:15:14PM +0800, Wenbin Yao wrote: > >> From: Qiang Yu <quic_qianyu@quicinc.com> > >> > >> All PCIe PHYs on the X1E80100 SOC require the vdda-qref, which feeds QREF > >> clocks provided by the TCSR device. > > This still looks wrong and you never replied to why these supplies > > shouldn't be handled by the tcsr clock driver that supplies these > > clocks: > > > > https://lore.kernel.org/lkml/aBHUmXx6N72_sCH9@hovoldconsulting.com/ > Sorry, I thought Konrad had convinced you. IIRC, he just said you guys were told to add the QREF supply to the PHY. That's not an argument. > If the TCSR driver manages these supplies, would it be possible for tscr > driver to recognize when it needs to turn vdda-qref on or off for a > specific PCIe port? Sure, just add a lookup table to the driver and enable the required supplies when a ref clock is enabled. As I mentioned in the other thread, the T14s has the following QREF supplies: VDD_A_QREFS_1P2_A VDD_A_QREFS_1P2_B VDD_A_QREFS_0P875_A VDD_A_QREFS_0P875_B VDD_A_QREFS_0P875_0 VDD_A_QREFS_0P875_2 VDD_A_QREFS_0P875_3 and it's not clear how these maps to the various consumer ref clocks, including the PCIe ones: #define TCSR_PCIE_2L_4_CLKREF_EN #define TCSR_PCIE_2L_5_CLKREF_EN #define TCSR_PCIE_8L_CLKREF_EN #define TCSR_PCIE_4L_CLKREF_EN That mapping can be done by the TCSR clock driver (which would also take care of the 1.2 V supplies). Johan
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index ab90aafb3..c3c725744 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4142,6 +4142,33 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v5_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .lanes = 2, @@ -4164,8 +4191,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4197,8 +4224,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -5094,7 +5121,7 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { .data = &sm8650_qmp_gen4x2_pciephy_cfg, }, { .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", - .data = &sm8550_qmp_gen3x2_pciephy_cfg, + .data = &x1e80100_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", .data = &x1e80100_qmp_gen4x2_pciephy_cfg,