From patchwork Tue May 20 11:07:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 892030 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EB0321CC40; Tue, 20 May 2025 11:08:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747739285; cv=none; b=Um47ub5tf2QD1/84IZdOfniYFsXEEdHA3sZa9wYc3EwwxTQy8XJoU9PHGgEehGitIaqmThyol3XrWWgHvpu6FAfYW651oIs+l1AKITG7drpKO3KG1uFjuRxmF9BV+SFJA2JPi+hwVvabmA3sumOXILGGP2xytcJvobTZ4ugMakM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747739285; c=relaxed/simple; bh=xwZIQDSTNK+pw+Q5pe4+iRBnPdFD3b8O4NvG/smA8JI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lImgLRU5gv7OZM1kjdiAKDm36hXZj6kQkfd/2JOjm2ZSAjBlP1KsmAbWcoRc56G/lPTZmszRW6X7w4YwShUAMdTDxe0Zaeo4WBUczydTGWueGqoTVjUx7tMc0HE7NZCpmQ8CYpwEBv6NU5Cebko6cAMv/21BELlBl2w044CClKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VLZBXcJ+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VLZBXcJ+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9180AC4CEFA; Tue, 20 May 2025 11:08:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747739284; bh=xwZIQDSTNK+pw+Q5pe4+iRBnPdFD3b8O4NvG/smA8JI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VLZBXcJ+DrVJKDSvFFQjYyLuowz7UwEEXrju/vm0Iu8EqrAAigfBHCtQj8JYPlCKm LSVfshUt2fVXV9BCdMKJW0T4L2lGgb2rmueQvnqJO6qxDMq7PLWhSQ97FzT5IRY7B8 sb5FGFya0Q6lF+8/z5j1FL+BSunhDLUYMwunhqhlEYVpNortfkruoVBs8+fp0xSm8O lR4sGqmenR4O1Gb5AuapQw/x7qSUy5RIU6+q9DrGX65NIFoxLgig6fCQ44jg8ZTrix 6kLJc4UefEAkYC7I5AM/Uin5AqseMR4fRLZhtIlQotC61oNeTpJD60VlBrJjqyAOVf H2WURJMu2sjAA== From: Konrad Dybcio Date: Tue, 20 May 2025 13:07:15 +0200 Subject: [PATCH RFT v4 10/14] drm/msm/a6xx: Simplify min_acc_len calculation Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250520-topic-ubwc_central-v4-10-2a461d32234a@oss.qualcomm.com> References: <20250520-topic-ubwc_central-v4-0-2a461d32234a@oss.qualcomm.com> In-Reply-To: <20250520-topic-ubwc_central-v4-0-2a461d32234a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747739236; l=3209; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=sf3v5naIm80OxSwfUeMCc12184DNVulDMvEQYLIwKj0=; b=WRTIHCm69qFRCYyq6a3aQ4laaJMIYr06rSmFdq09TebbYapUDQhaoKZKxxM+2UEeSrDRe0qKd kXB1XpOc/moDdohFD6WcZ/mu7D7gnrEfmTboDianIoymYqXNaoxEy8t X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's only necessary for some lower end parts. Also rename it to min_acc_len_64b to denote that if set, the minimum access length is 64 bits, 32b otherwise. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 32017e2730a9059a16ef551363660b72d7f991c8..6dd5281678a5f31be9c59e3b247cfd5a34341ec1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -592,14 +592,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (IS_ERR(gpu->common_ubwc_cfg)) return PTR_ERR(gpu->common_ubwc_cfg); - gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; gpu->ubwc_config.highest_bank_bit = 15; if (adreno_is_a610(gpu)) { gpu->ubwc_config.highest_bank_bit = 13; - gpu->ubwc_config.min_acc_len = 1; gpu->ubwc_config.ubwc_swizzle = 0x7; } @@ -645,10 +643,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.macrotile_mode = 1; } - if (adreno_is_a702(gpu)) { + if (adreno_is_a702(gpu)) gpu->ubwc_config.highest_bank_bit = 14; - gpu->ubwc_config.min_acc_len = 1; - } return 0; } @@ -668,6 +664,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; + bool min_acc_len_64b = false; u8 uavflagprd_inv = 0; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; @@ -675,22 +672,25 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) uavflagprd_inv = 2; + if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) + min_acc_len_64b = true; + gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, level2_swizzling_dis << 6 | hbb_hi << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | uavflagprd_inv << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); if (adreno_is_a7xx(adreno_gpu)) @@ -698,7 +698,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) FIELD_PREP(GENMASK(8, 5), hbb_lo)); gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, - adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); + min_acc_len_64b << 23 | hbb_lo << 21); gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, adreno_gpu->ubwc_config.macrotile_mode);