From patchwork Tue May 20 11:07:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 891349 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AED1627C84B; Tue, 20 May 2025 11:08:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747739299; cv=none; b=ZuFp9pL/bI3kH46q/9blEYxPteZCyBt8qEDaq5boAx6ZplGT/VinI85JubsscNAlhwpGdX7dTrqEq3ByCVN7eI4zaDBAr9xYNrRO7ybzlXhgXHfzQHKsmhjeKFh5LTgO8BYgTIv/rH+/cwIAf4f1MY4AqpM/niQFZEoNWNiSw5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747739299; c=relaxed/simple; bh=il2ZY/ImJEY5uQ0Fej2VwgjSUYexMYWZIXkpwYUGoGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nDI+dBDUhd9nIUII7RjdUHYQciFGVuH4sNDaBw1kUpX0WRcL181YeIO+sL7ZGx/c8+o1rY+MyZdU/xByey9X1dBokIu7PGvA7ALF+O6T8EAj03zDASFncMGj+wvo1pqb2VpPvoyRUiE6IG8MJqo1dDib06jMWzwdreNbG+j+iUE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mDE8arhi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mDE8arhi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57A03C4CEEF; Tue, 20 May 2025 11:08:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747739299; bh=il2ZY/ImJEY5uQ0Fej2VwgjSUYexMYWZIXkpwYUGoGo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mDE8arhiWSFwJD8LIKrV40aq8lKjEcsII8Ngvtc50o3Ds5Tvk/VlqcPrU8vF6lQdC vkccHTPm7JlyOV95yEb+eqbPQPCF4VDTkR/0hH2ccC1lE1kT9QGFYgnYJyUY6PtiDj DYPJdB9L9H5oJ3h74holyhiSTg3BPy+wzAHgBmsBdhXvlOL/ox8QjEtyQBuLel2Ozf Z/gTBVXRy5+0V9cC1NDJb637ob3vKwO6aTy1VFQMPcSEYuXAlJ/gH4OfCetwO6jok+ ROdiTfGtCOt2DuQEXjvv1zxpnudgZs7OSWq7q1897qInCuu6tn1X/zRByS/fsZsHtN CxlwaMCkA/hyw== From: Konrad Dybcio Date: Tue, 20 May 2025 13:07:18 +0200 Subject: [PATCH RFT v4 13/14] soc: qcom: ubwc: Fill in UBWC swizzle cfg for platforms that lack one Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250520-topic-ubwc_central-v4-13-2a461d32234a@oss.qualcomm.com> References: <20250520-topic-ubwc_central-v4-0-2a461d32234a@oss.qualcomm.com> In-Reply-To: <20250520-topic-ubwc_central-v4-0-2a461d32234a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747739236; l=2912; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=E5fczafhh/uEXMHOyVRmVoztYqjDLeEbZSi/EodcxVA=; b=xRWcocgHokMh3EOH6pf9gGzSATabifJMAWSp3uQbzKbNp2DrZaCucI6GiPlB3j07xO83JA8Zw 9RZpqND8sv+DSJ6xs860vsem27DNqXKuGSiTqDPSu4aXo6wnMXDv2Tw X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The UBWC 1.0 case is easy - it must be all 3 enabled. UBWC2.0 and 3.x require that level1 is removed, follow suit. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/ubwc_config.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index fe874ccd8df6acb4fac65f7d261afb05861117c2..a4b730dac6c4aaa609d41b2782c9dc522387d8dd 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -15,12 +15,18 @@ static const struct qcom_ubwc_cfg_data msm8937_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_1_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data msm8998_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_1_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, }; @@ -70,6 +76,8 @@ static const struct qcom_ubwc_cfg_data sc7280_data = { static const struct qcom_ubwc_cfg_data sc8180x_data = { .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_3_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 16, .macrotile_mode = true, }; @@ -87,12 +95,16 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = { static const struct qcom_ubwc_cfg_data sdm670_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, }; @@ -118,6 +130,8 @@ static const struct qcom_ubwc_cfg_data sm6125_data = { static const struct qcom_ubwc_cfg_data sm6150_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; @@ -133,12 +147,16 @@ static const struct qcom_ubwc_cfg_data sm6350_data = { static const struct qcom_ubwc_cfg_data sm7150_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sm8150_data = { .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_3_0, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, };