From patchwork Tue May 20 11:07:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 892033 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A45427CB0D; Tue, 20 May 2025 11:07:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747739258; cv=none; b=KuobM1R3jWBbvAm9rATsZis644W8AuBHuktulqXrsgK1QpZMufqA1GULvJADRzqe+xVDsazrdPQ+lIs0+cwxUGaHplwD832BW7GatXRF72+i74ielm93w/k0zKXXnWYZxrCrA+3bHy5TDuHhqDX8eTc5KTHRwsQoFQQ5XbPkMhk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747739258; c=relaxed/simple; bh=tFc9hug2b7fXl6hOuuxgkah3z/v9PQJg3mUq+erHT68=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EIdzSlDRbI2L/p1Uxwt4sH9S00VurZA73dbeo5h2JR8cOMeQjiCi04RtUezKrhQd1ob9/zBLMurO8EArTF83JGl1JvQccWHgM0G5HOJfWfNZB0Lj1QMbfFZK1qR9iKhQTUiyeX757gxvv8PiaEqindWo9PhiiCk1JHu0YTtIBt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L7Vo1JZd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L7Vo1JZd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30FC1C4CEEB; Tue, 20 May 2025 11:07:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747739258; bh=tFc9hug2b7fXl6hOuuxgkah3z/v9PQJg3mUq+erHT68=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=L7Vo1JZdMbSbyzr+WVa+cQd0QSJwf5kAog0K+3+ynLf97YhKRqLsRUW/W6+vTqBUV yGR3JHbVz1LVyrikVN8f5TzVAAZILDg1iKsDEjfcf2B8zLohxph+WAdcT7oA5bFhNL 6QEefdwN5MzTJyq/EnmKFIq+4L6eiZN3Wt0sehMRt0Zd6prQAC8zWGM6GJHkMyrpiR +n0udDUqFgK82qymm9QdVkqPH8YhSsmGzpt5I+D+DrD9MJfqor0GDdVk10ErcjfM7Y vIrEnIYX17hJ2O4oyl/rwDygQe+F7Dq/JZuVqnFR0zO0GzB6vaxoot82tj03MCUP8w 8cxXH+0i5J+WQ== From: Konrad Dybcio Date: Tue, 20 May 2025 13:07:09 +0200 Subject: [PATCH RFT v4 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250520-topic-ubwc_central-v4-4-2a461d32234a@oss.qualcomm.com> References: <20250520-topic-ubwc_central-v4-0-2a461d32234a@oss.qualcomm.com> In-Reply-To: <20250520-topic-ubwc_central-v4-0-2a461d32234a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747739235; l=2657; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=CuuD8qViyGRCfouTGuJaUY+h/7zt6demaKxkARZ/ecE=; b=h02w63c3aoSF17iUnMsz+mkgVLvGFnXuEPEu5s2RnxTVooSDVPIW7660+9OAglwQx0AAJf1Bq KzUN8I4T7uCAqBkNHT9XjzV95cvfOVnyel/kD5c7IkHd0cu+iSqRx2I X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Start the great despaghettification by getting a pointer to the common UBWC configuration, which houses e.g. UBWC versions that we need to make decisions. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index bf3758f010f4079aa86f9c658b52a70acf10b488..4399e69bd5156c9d8c6a17213ae02ae03ddae529 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); } -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { + /* Inherit the common config and make some necessary fixups */ + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(gpu->common_ubwc_cfg)) + return PTR_ERR(gpu->common_ubwc_cfg); + gpu->ubwc_config.rgb565_predicator = 0; gpu->ubwc_config.uavflagprd_inv = 0; gpu->ubwc_config.min_acc_len = 0; @@ -663,6 +668,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.highest_bank_bit = 14; gpu->ubwc_config.min_acc_len = 1; } + + return 0; } static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -2546,7 +2553,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); - a6xx_calc_ubwc_config(adreno_gpu); + ret = a6xx_calc_ubwc_config(adreno_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + /* Set up the preemption specific bits and pieces for each ringbuffer */ a6xx_preempt_init(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a8f4bf416e64fadbd1c61c991db13d539581e324..06be95d3efaee94e4107a484ad3132e0a6a9ea46 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -12,6 +12,8 @@ #include #include +#include + #include "msm_gpu.h" #include "adreno_common.xml.h" @@ -243,6 +245,7 @@ struct adreno_gpu { */ u32 macrotile_mode; } ubwc_config; + const struct qcom_ubwc_cfg_data *common_ubwc_cfg; /* * Register offsets are different between some GPUs.