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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:04:12 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:33 +0300 Subject: [PATCH v5 14/30] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250522-dpu-drop-features-v5-14-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2585; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=aJLcwGKHuUuyJyLVdSDXU6TlIm9ioIVYSavHMvjyGfs=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ4Z+yd8mTk2bq+c+3TmX5ynanBR5/773oyf8stvcI+eqP 5xp8ra/k9GYhYGRi0FWTJHFp6Blasym5LAPO6bWwwxiZQKZwsDFKQATuRTHwbBc9W6r95vWw+vO fEo33H74bI/AE3GlkzUmPAceJlx7W6nltuSGa/Cfnu9PgpfZ8dQ5y2d4WaU8/cZoa53SWLSzhXH axj0qGb67lFL1Cu4GN/Z1NzzNDGRqeF5/ZL2Ng/qpIzOebbr7bRpf8LJivVq25Nec3SeMQzJbeh iqt/zjqxS9Nfv+5t8Wa5sz/Pivp8h0MDoYn7Ew+/5rsrqPzOlGreCOWhcjsfu3jbxaan77z9B49 ZdP1v3L+rzV6mJZm2t3OWxqVZVaEh/HzXzAo0bXgemC+/3WegtTnRB1c9/6wDVXt0lJ3f/Gu0aZ m3cjr/1ZFr2+vrTST6amdU827Co+kc5yOMKYYf/j57MA X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 9oq_vgnSgY4zkV-OFx1eFtKszJlYCQtF X-Proofpoint-ORIG-GUID: 9oq_vgnSgY4zkV-OFx1eFtKszJlYCQtF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MiBTYWx0ZWRfX7cP9sXgG2c3D bWnKelovLhHa9qyG5GGMnw/Q+Hd6FzppqzHSQbapOaj6Jff/g0AV1it1cpYbbkEa/kn0jt7Fxt9 QGkvLiBj8GK/HwVmXsZ13G5HTYNICbed7NLA+jnye713y2BcP/jV/hmcicWrNVvCQvirKC7Ccbg dFFS9PlR1+L0dqSixuUw1YErNWpggbcEQXevD6cCRXyJzqMpCmiWGWhaQFrpSbtpEL/egws+f3m dXZu44TKiu9N6qgmUzBtU1GTHgwTj+jWAFwAxa0aeh/qAZ8zf+YOBlTRQ7ZM1+xqmZQRjJyVwjs 9dD11b1EEWguvjfCkCIBPJDhmWMtCjVI88CQmgslbvuHoKiQ6muPeqCSO3VWztln+EKu0TRMWrU cIwP6P3TRGOIc6jvINA7rDQuwr7EqxvLK/oYzKbI2iAgSje/hjNzvI/W+CMB4PR3px8RHn0O X-Authority-Analysis: v=2.4 cv=R7UDGcRX c=1 sm=1 tr=0 ts=682f752e cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=z6iiZyybfqEMMI01lysA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 mlxscore=0 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220192 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 +-- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 1244dd59648d11123c507a1369f28f952d047fd5..4482f2fe6f04e58408b55994d885ea1c717c6a07 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -105,8 +105,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) #define INTF_SC7180_MASK \ - (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_STATUS_SUPPORTED)) + (BIT(DPU_INTF_INPUT_CTRL)) #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index bf6b2392efb47fa8c3e3c5d17f1a72341872e18b..e1c6df3a3b72ffb5a816bd18266a35abe723fbd9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -143,12 +143,10 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which * pixel data arrives to this INTF - * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL = 0x1, - DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8f9733aad2dec3a9b5464d55b00f350348842911..54c2e984ef0ce604e3eda49595d2816ea41bd7fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -308,9 +308,8 @@ static void dpu_hw_intf_get_status( struct dpu_hw_intf_status *s) { struct dpu_hw_blk_reg_map *c = &intf->hw; - unsigned long cap = intf->cap->features; - if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) + if (intf->mdss_ver->core_major_ver >= 5) s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); else s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);