From patchwork Tue Jun 10 08:37:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 895303 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3827C27F161; Tue, 10 Jun 2025 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=N5F3YGEX/kcIWlYetetFyooO9Q2QXGDsPSaxs1TFT6pk4VEyLlD7+fr3egSSeZK5fcBOBS3VAhdtS6imRcXa0fkXAUqE3kW+O5pFvF5GvgdN1ygxagOOMrx2weK31Z5DGr5VT9KrmklzMQebvQToaY3cUIjnc2kaw+QdNKSvPOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AeM2x6naDnHA4/iitIwJH9MaqFlqG9N9JHMaOZP2bWFupGSlARqhhLmD59dSHqm4sK2d9zutnMuKGAmRn0brIqkgGklYkpj2F/U65cVaYeEpqi7YfjHIyz4XwCbVKkbqEBDqjTjThRAUkMQvI5AVkwlDn6kuFVcD46CTWW/T4Xo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XjoAbiSm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XjoAbiSm" Received: by smtp.kernel.org (Postfix) with ESMTPS id B975CC4CEF8; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XjoAbiSmg1Po7tpwTGAmWWtYTbiZ0LXLYE1v/BL3GqwqJmZ9KsjXUOmRb79WY7Byc QJv6vjNMQBGzp6R3FCyrZkQIjjTigQ5kf5W/FmAoY8w4a2oNuZtetTE7kt0ZmJdNvJ 8eVwqhfil2j3gklSOVDJj7+Di3LwkGEEaFBsv12rUL76LDhF35tZsiO7C5m6K8Dmjr SlSWrmMZ5uHdZhUJdku7U9qol75pL5nFncpfRItKd4NUehTEZKalH3NhCGWG3ht6iZ KsQVsCCGWpqLhUu87P5wnDqSRz7LcyJeJdkHnnlt2rLmIJHvIsr62gzWI7VJoc3qsL veOzGQtctxOfA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1350C5B552; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:58 +0400 Subject: [PATCH v5 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-4-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=1519; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=jA4BQsaw0tlEf36IZrwvZtR6C1am2pcwyAdrevsj4Hk=; b=hSdTUjtHpj86cr4Uswl07p/eGEBxIRuMBAke+RvCCCJbKkJroLYukxiZGqC+81GFvdhl/6/cy QmPPrAlvwkPCk1J1YNDgekzSGJVfB+izSE0U42LnirA4BF3JajsjhEj X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce47a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status = "disabled"; }; + mdio0: mdio@88000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00088000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + + mdio1: mdio@90000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>;