From patchwork Wed Jun 18 14:32:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 899137 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E09827E1C3 for ; Wed, 18 Jun 2025 14:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750257211; cv=none; b=MGgV6T501pEKb2vj9ZbsroePf2fYkMOboymYPzfPViG6WVBDbOE1kXxiCwVYmH1JQEllHVL/7tWT/ZZbMD66udqzTVDEivW486kqxHwGZLFD+iguA+nAebfvViw+hLnYWTJ/TR9oqOwIMpMhK0QRtRbDTO29Pyg5SsOAca3O6kM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750257211; c=relaxed/simple; bh=bDt93fOPMIU1TrFk4w98DkGoRUoI6srG26oyPVGDWKo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N//joVRYvAHVu357SnKebwRQAE+uM9vf5QR4fmOgGdYc6oiLUDtkR5Ju8GYU5YDH5PPHrc5JqNYiHc9X7ESmlGSHhJ5wAwyorju1zQIAGkviXUUtwA+jtT9V2Q8d1S+2NE5S/77eebISwzvoElVwqz0bElBFT2fY+qYHwlXb60A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VsXK0Z5i; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VsXK0Z5i" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-adb4c022f77so106459666b.2 for ; Wed, 18 Jun 2025 07:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750257208; x=1750862008; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8Puo1BSKXfvASrz8ngnnVFm2/cTt2FMnvm9GvL4gi3c=; b=VsXK0Z5i+r5/3dfNuAd+ZGV/O+iUi6+5qjKeRK33xqDe6XZhXc/l4CO5lTNT+YgTvy Nx2CK//R0t/vn3aJ1mfOm4OcmMwzOPV6KtOr5BWsfnTGzXZ6l7GyTUnDIqZLH1WH0ZR0 cVpH5UDgONByRBMSazp2UWfsBk/ZGI/AYleh1c1EARC92njO2zMwBIivSrcxdXJz8RsD 3ddzBNqxwDHkP1RaTpfqGsqK5PFFQS2DtZHJ/r1aFEU/zttiTXCiwV/AN25ecuVVR9w3 p/pPWIi6Y0vWY+Z9/7MSOxXTAck6kS1BmDEP1dSmc6uPAwwt1PlbJQGa7ssNserh1Q+o tllw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750257208; x=1750862008; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Puo1BSKXfvASrz8ngnnVFm2/cTt2FMnvm9GvL4gi3c=; b=MC+t31/tkxR/ejamYYDaUdYqCjnH2OJSpgzZg9nPE8iUunuY3DeOw5ugKQCaWRzH8e qr8DuUtDb0HYs9vZBcx2rlAUkOSthAbePNX3Xq64v9MTnHVAlPQDZJNf1ucHcDWmHnpV wu+nY6EOy+LMumGKCTxp/bOa+oU7wCLfJ7NLqIv7CotIKrZ+i3I7x8veAXVL/arzmF+s tZ5eWODXECkpn9h7pmV16QTCJGv2m9P6kGjNVJxW7TLf+8u0ksZy96/QJ9YUR4hU7I11 2zZ42GYo7wk/RYs3YC2fRwAKub91M/ygaMeOz7FBSQDdbzMAe0PYNmLrle1vY3s69FH4 BqzQ== X-Gm-Message-State: AOJu0YxbJTZ8YSYOM+r714gvcXqwbBrouq2twS+bQmJ+701lThrzlicI zgvQkcOgULYB1KKdcrX8fFEPV1uStkpgcUqtx+vyGC+E8Y9bV5EKKIVSEOiXBQjDnBo= X-Gm-Gg: ASbGnctvbCbwqxhwhLPAXw90n8CylZn8XfG7NZ5x7PUD+QdphbeWEsLdwWDmV7TTHcy bPNlloQAgRuSmOBOongY6hkF8plilxFyRCAZrqdTV0xQYDg5mZcTYNRpJBjV3VHmJhgywWR4gO6 5S93nPkjvKpPmUrGovSKo/BV7tReDW/eAHvAAkiSrJqjZLZVh2EfQUReYO+YB0OSND/oaZnCj1n 0OebQzrD99a/ni/T9/0eLBzKEo6EV/PQu9qvqcbkzr9U5lHi28kvV2iVWmJUmev7Q8RG9DHV+n/ vBkOieFQlyf8R0a/jt9AZb7Wl+bUAls7U/fBJMWwDoKBCsKlliLJYYQRHwO8QTdYuSIpN7VXihz S9RlXqC0= X-Google-Smtp-Source: AGHT+IGgN/aWMMV9BGSGvQ6W4soFxE3Wti2T2mPFLqBAEOnqGEalMHBUa3BErX1TKSwWTfe2YaGW9Q== X-Received: by 2002:a17:907:3c94:b0:ad2:23d0:cde3 with SMTP id a640c23a62f3a-adffb27b554mr273348666b.15.1750257207559; Wed, 18 Jun 2025 07:33:27 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adec81c0135sm1052257566b.47.2025.06.18.07.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 07:33:27 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 18 Jun 2025 16:32:35 +0200 Subject: [PATCH v7 06/13] drm/msm/dsi/phy: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250618-b4-sm8750-display-v7-6-a591c609743d@linaro.org> References: <20250618-b4-sm8750-display-v7-0-a591c609743d@linaro.org> In-Reply-To: <20250618-b4-sm8750-display-v7-0-a591c609743d@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10151; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=bDt93fOPMIU1TrFk4w98DkGoRUoI6srG26oyPVGDWKo=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoUs4e5zKy91RDvgwO12wZAfsNu2ncXHVq1uV6s sOwGdCjTJeJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaFLOHgAKCRDBN2bmhouD 10+XD/9d+4rtqtoafs5le+CiKjfqovjTm98978QrxZxd8ZmpKB2cU14lYFoftKFTXAVJOypHwQU UOUfhcaPzo0d2JB00TdhZZp28LTUWrpDW9fHSHu9Ynq5ZfwY4py9Y3DCkibh0buzPYonTBVE44Y OzlQkMwetzFrLMiMZIxSYivTAzeu9ldYGEvSgK3Mu6oOCJRqSMfQlYJVS5zKhlWV0jrkA2NoXfk Nn7AoNRzXUzRskN7nO+m55DALGOP6HpRoZRf3WepGkgz1tHslvtYkx4TQDzxZlOxu/x5JBgSYam dqeIpa3c7fgC7kokFg4/kfrjbCvK/FGCoueqk0BBEEFn6IUENK5NoOwy3u5Xh/8yVVaU9DNViOR q7Ma/cN4q33qxH/yrqaiJpq+g+A90wpxP8QXDoooarozYA8vZe2DDcvqnMkQho3Cz5QjavpaK30 7kF1TX8SV4ukql+OJh4w9+wLicVlhy886t8Owv9aoNwIeX0OdPxt+iPZci/jzTXbVtcWNVPRZxf ZZh5fy6AMAmBmdv+svpjTftf9i3OfxmGLAX8OpqFjLJsQk8ZhTAMoPhemtPTY6WbzxizkDu8yKc gZ3nsZFrXDf/VPBfEmfy4BKDvhTh0bVd+WlI4RifeoJV/o6+zNX5p8LEOU5bj/RlYn0RLvteeWC pBCumR6VdFEISqQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an incompatible hardware interface change: ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their offsets were just switched. Currently these registers are not used in the driver, so the easiest is to document both but keep them commented out to avoid conflict. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Fix pll freq check for clock inverters 160000000ULL -> 163000000ULL --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++++++++++++++-- .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 14 ++++ 4 files changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 5973d7325699bf5fc67c4cf93fcaf04abb618b46..221f12db5f8b7686b2f37524322ea3e118f503b1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -597,6 +597,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_4nm_8550_cfgs }, { .compatible = "qcom,sm8650-dsi-phy-4nm", .data = &dsi_phy_4nm_8650_cfgs }, + { .compatible = "qcom,sm8750-dsi-phy-3nm", + .data = &dsi_phy_3nm_8750_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7ea608f620fe17ae4ccc41ba9e52ba043af0c022..c558f8df168479fb91b65186ab96cb3de4e33d9c 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -63,6 +63,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index c19890358b7479c85c793aa7470904127c2d0206..8c98f91a5930c9f2563a6b4824690ceef56987c0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -51,6 +51,8 @@ #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) /* Hardware is V5.2 */ #define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) +/* Hardware is V7.0 */ +#define DSI_PHY_7NM_QUIRK_V7_0 BIT(5) struct dsi_pll_config { bool enable_ssc; @@ -129,9 +131,30 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config dec_multiple = div_u64(pll_freq * multiplier, divider); dec = div_u64_rem(dec_multiple, multiplier, &frac); - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { config->pll_clock_inverters = 0x28; - else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (pll_freq < 163000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 175000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 325000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 350000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 650000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 700000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 1300000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 2500000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 4000000000ULL) + config->pll_clock_inverters = 0x00; + else + config->pll_clock_inverters = 0x40; + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (pll_freq <= 1300000000ULL) config->pll_clock_inverters = 0xa0; else if (pll_freq <= 2500000000ULL) @@ -250,7 +273,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) vco_config_1 = 0x01; } - if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { if (pll->vco_current_rate < 1557000000ULL) vco_config_1 = 0x08; else @@ -620,6 +644,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); + void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_7nm->phy->id); @@ -629,6 +654,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) break; case MSM_DSI_PHY_MASTER: pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; + /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) + writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5); break; case MSM_DSI_PHY_SLAVE: data = 0x1; /* external PLL */ @@ -907,7 +935,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Request for REFGEN READY */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); udelay(500); } @@ -941,7 +970,20 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, lane_ctrl0 = 0x1f; } - if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (phy->cphy_mode) { + /* TODO: different for second phy */ + vreg_ctrl_0 = 0x57; + vreg_ctrl_1 = 0x41; + glbl_rescode_top_ctrl = 0x3d; + glbl_rescode_bot_ctrl = 0x38; + } else { + vreg_ctrl_0 = 0x56; + vreg_ctrl_1 = 0x19; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (phy->cphy_mode) { vreg_ctrl_0 = 0x45; vreg_ctrl_1 = 0x41; @@ -1003,6 +1045,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) || (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20) writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4); @@ -1117,7 +1160,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) /* Turn off REFGEN Vote */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); wmb(); /* Delay to ensure HW removes vote before PHY shut down */ @@ -1384,3 +1428,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = { .num_dsi_phy = 2, .quirks = DSI_PHY_7NM_QUIRK_V5_2, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_98000uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V7_0, +}; diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367..4e5ac0f25dea856a49a1523f59c60b7f7769c1c2 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -26,6 +26,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + @@ -191,11 +192,24 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + +