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Mon, 24 Jul 2023 17:22:27 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::5111:16e8:5afe:1da1]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::5111:16e8:5afe:1da1%6]) with mapi id 15.20.6609.032; Mon, 24 Jul 2023 17:22:27 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v5 23/25] iommu: Add ops->domain_alloc_paging() Date: Mon, 24 Jul 2023 14:22:13 -0300 Message-ID: <23-v5-d0a204c678c7+3d16a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v5-d0a204c678c7+3d16a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BL1PR13CA0200.namprd13.prod.outlook.com (2603:10b6:208:2be::25) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH0PR12MB5252:EE_ X-MS-Office365-Filtering-Correlation-Id: 18473151-854a-4864-6726-08db8c6a892e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iWFp9rI7d3uDeq/1XeiqAnmuur3Vi4ll30Q0UfP2Uc7rsBLz/xeZewQ9SyQ6Y0Ur4qWfuD0uKMWw89vUgZ7FLTs6hPFd48M7dPkIdVZx/F3FYFCFTY3OgDZqvyXNwtCKsAl61HBTeMLZ1SGriQTuS+s2ZgmJQSDDMss6OZA1mVf36b50VbAsUu4K3Bdq6weZRDPqhg4dfNxWAQvesB5/QNcXwr1tjt4/UqRZEfTPEbikxjvYwKrCnEsnbz6dbTcLFVj62RVLtlvnZFWQzWSud6kTHeWm84sTVObH9MYJCozvjugih/UnwPa9jxedqzEvTssgQCv8NV8uaMgwuYbXRA6srgKQt/XH94S5m3GLhUn5MOsXceZEYABEiuFy2FXC8h7w4nEkj/u9ig2pd/ms8lO4wIEX/REd72lD3cPCdkLW3q9eoEnM4XXAeza6e1O6SBWPcm3BI3gGanHFEHh1dB76hp6xb73j0+i5UxQte1qz4f4td1pMGVhvYcV0L6iX3GfXkH07meVnl1RGK031t1HRRQytfb/nSuRlaXnm2YkroFHETWEGADrmXKeq2eGlt3UftMgb8xNrgbxoyJ1ytTllvsLfbi9104wG7WaU1GOJo7vdGyBigOzJfzF5ccnb9ryRxGOHU+nUYbZb6RuBZG3/xEIhMzLTKat9lC8QC6vNmZXMQ/15qZCboRTIL0N9yCtuNn1ZtNDr/+irnDbKnhdk/EABkca1dPO7tL+msNAWTcDPWAYMjIhPE4JsjMoqzh17pc9ODb+uGdbGixwDNj9eoveJMs/LBx86HjMSdCh4JkpLCOQyjjBC1m+w3MIEWM/1X2rXeBDSKXPNBuDVg6UEWOfes4XEAeZeVEvvjfwDbgvWbK4BL5LloQ5cqocL/mC9dorn4GCv4iT6e8umP8T948UrqZkCUDnojGhpallFVOeW5qYe7RabxrmXveSmkxEN+nWG5oa4TqHu8ebom5CZtajNoMl7l54B/HgsfhJR0V0mntvI7LTflxQu8o0ijz+5A4jGxpIzNM07JPPPidzdCCDemxHS9Yak3qG09NiS+vr5jedtAp4gK7+Cgs1m5NiLOVVEGzyjAoea/4R85ZrDak626JOgaFrQMXSjvS1E4l3EAmOgq+jOnGAdvjr8dvkjChmOBBLf3M4b4FyYa3YqiTmz4TjPy8H0K8Fmw/zRzH4WxcRDpE0ItbxKB4jd6wm0sjXnsnAf60hlcICGFT+tl0boCzLjU+lfuxgEC0+GiiB9/5fkvWU/N4ptPLOanIawm1f8a+n+I9JcHJdyS6ki/1L3vo7yfsLSpr+PXDgbtjSO/bQ3SkP/Y79s3EhfW2WpJpmV4eD043rahBF0IACDpkcxJALI+OnGVxSsYSapdsvmNNqqCcgMfwY06uWAwSlownqajD0rg4rh4SIEXGDddDmNjzza4dGLKZTnFGzLrof7RCG64+8aXN/619L2fUBgYGZkV9Lwg+H5EOEaVcbWOgqUVZK6MQOHwsx3lRw7kHpz3w3qqJmWNF4l4rIq3iNVhoqgJJVZ/4pPgB6IIwrvKbrBNrO2s2Nw25m7cn2Xg9woSOyI4C+WEvCLFMBn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 18473151-854a-4864-6726-08db8c6a892e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2023 17:22:20.1360 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PPwQuQppZvhGwrB8gPAe0F2Ud4zRR1fMunX9VQRoOIbN9XHsiSM79Ydlni3nT2Xo X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5252 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This callback requests the driver to create only a __IOMMU_DOMAIN_PAGING domain, so it saves a few lines in a lot of drivers needlessly checking the type. More critically, this allows us to sweep out all the IOMMU_DOMAIN_UNMANAGED and IOMMU_DOMAIN_DMA checks from a lot of the drivers, simplifying what is going on in the code and ultimately removing the now-unused special cases in drivers where they did not support IOMMU_DOMAIN_DMA. domain_alloc_paging() should return a struct iommu_domain that is functionally compatible with ARM_DMA_USE_IOMMU, dma-iommu.c and iommufd. Be forwards looking and pass in a 'struct device *' argument. We can provide this when allocating the default_domain. No drivers will look at this. Tested-by: Steven Price Tested-by: Marek Szyprowski Tested-by: Nicolin Chen Signed-off-by: Jason Gunthorpe Reviewed-by: Lu Baolu --- drivers/iommu/iommu.c | 13 ++++++++++--- include/linux/iommu.h | 3 +++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index bc8b35e31b5343..5b5cf74edc7e53 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1999,6 +1999,7 @@ void iommu_set_fault_handler(struct iommu_domain *domain, EXPORT_SYMBOL_GPL(iommu_set_fault_handler); static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops, + struct device *dev, unsigned int type) { struct iommu_domain *domain; @@ -2006,8 +2007,13 @@ static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops, if (alloc_type == IOMMU_DOMAIN_IDENTITY && ops->identity_domain) return ops->identity_domain; + else if (type & __IOMMU_DOMAIN_PAGING && ops->domain_alloc_paging) { + domain = ops->domain_alloc_paging(dev); + } else if (ops->domain_alloc) + domain = ops->domain_alloc(alloc_type); + else + return NULL; - domain = ops->domain_alloc(alloc_type); if (!domain) return NULL; @@ -2038,14 +2044,15 @@ __iommu_group_domain_alloc(struct iommu_group *group, unsigned int type) lockdep_assert_held(&group->mutex); - return __iommu_domain_alloc(dev_iommu_ops(dev), type); + return __iommu_domain_alloc(dev_iommu_ops(dev), dev, type); } struct iommu_domain *iommu_domain_alloc(const struct bus_type *bus) { if (bus == NULL || bus->iommu_ops == NULL) return NULL; - return __iommu_domain_alloc(bus->iommu_ops, IOMMU_DOMAIN_UNMANAGED); + return __iommu_domain_alloc(bus->iommu_ops, NULL, + IOMMU_DOMAIN_UNMANAGED); } EXPORT_SYMBOL_GPL(iommu_domain_alloc); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index df54066c262db4..8f69866c868e04 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -233,6 +233,8 @@ struct iommu_iotlb_gather { * struct iommu_ops - iommu ops and capabilities * @capable: check capability * @domain_alloc: allocate iommu domain + * @domain_alloc_paging: Allocate an iommu_domain that can be used for + * UNMANAGED, DMA, and DMA_FQ domain types. * @probe_device: Add device to iommu driver handling * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU @@ -264,6 +266,7 @@ struct iommu_ops { /* Domain allocation and freeing by the iommu driver */ struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); + struct iommu_domain *(*domain_alloc_paging)(struct device *dev); struct iommu_device *(*probe_device)(struct device *dev); void (*release_device)(struct device *dev);