From patchwork Fri Jan 28 07:47:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Prakash Ranjan X-Patchwork-Id: 537645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17573C433EF for ; Fri, 28 Jan 2022 07:48:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347082AbiA1Hsk (ORCPT ); Fri, 28 Jan 2022 02:48:40 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:46720 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347076AbiA1HsX (ORCPT ); Fri, 28 Jan 2022 02:48:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1643356104; x=1674892104; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7kckOmRKyq54j2yB6AzUrEcAKcHonOPFGbtH7xzTgzQ=; b=yGyRgtcK8zzjG5L41v8ZUDgHgNWlbcwwn+Pcr/7dblH3VK50JzhlN4nh KiWNcTjSQCzVSkFk1pU6jwEG34/o6aD+RG5pm7AE+3p/2sgErHNLIhf+a Ickr64R3YUCEMYdluwiWIpmOqlYRK+EIBWJ1uPZh4d6Qwl8aO4supRwCL 8=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 27 Jan 2022 23:48:23 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2022 23:48:23 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 27 Jan 2022 23:48:23 -0800 Received: from blr-ubuntu-253.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 27 Jan 2022 23:48:18 -0800 From: Sai Prakash Ranjan To: Andy Gross , Bjorn Andersson CC: , , , , Vinod Koul , Manivannan Sadhasivam , Rajendra Nayak , Prasad , Sai Prakash Ranjan Subject: [PATCHv2 9/9] arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node Date: Fri, 28 Jan 2022 13:17:16 +0530 Message-ID: <7995d003b77d5e066658af5b2cfa22ccb40b6cf7.1643355594.git.quic_saipraka@quicinc.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SM8450 SoC. Signed-off-by: Sai Prakash Ranjan --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 10c25ad2d0c7..5a3d050b94f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1102,6 +1102,13 @@ usb_1_dwc3: usb@a600000 { phy-names = "usb2-phy", "usb3-phy"; }; }; + + system-cache-controller@19200000 { + compatible = "qcom,sm8450-llcc"; + reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; }; timer {