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[209.132.180.67]) by mx.google.com with ESMTP id a9-v6si14053314pgn.177.2018.07.09.04.44.37; Mon, 09 Jul 2018 04:44:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hAup5eMo; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932881AbeGILof (ORCPT + 13 others); Mon, 9 Jul 2018 07:44:35 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:37145 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932869AbeGILoa (ORCPT ); Mon, 9 Jul 2018 07:44:30 -0400 Received: by mail-pf0-f195.google.com with SMTP id x10-v6so3643810pfm.4 for ; Mon, 09 Jul 2018 04:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=AsozHnJmlM1Of3480z5nTOd6XCOnsdEnjdMHZCjbbAY=; b=hAup5eMoPxA523Cjg6SMQConJmXEjj54Sk0Me6o3bkRNSYA0WI2FFe8s4aiivtMIUq lXK8/7jo0zC9YXvUDf15ho1TLOdTyZAGe8OvJ9PklF3kSrQsrRMokVlxgpuODfthfg/a njknPWlYuOdnlpRoHlHFseyyQBDpkWfNycfLE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=AsozHnJmlM1Of3480z5nTOd6XCOnsdEnjdMHZCjbbAY=; b=BtKXno+U0H8OEUUtezA0xdIMVmh+ziGvW/i2SxEzcgdBr2QAmh96ftc/CsKZH987cd 9fiM0dn/RYlmKbGnrJ0SA0LyAOMJeyULE6p3rYld0qw5Dj98NzGuotFWZ1mxoE2Ee+p3 FSdyaq5I39URNnAoTAccXUZkRqz7pfYVaGp0+GPu7e+QFwCPSYd4ZxZGCHgyoISXxXzV B86v4o2aArlQZk73hHgy++HhmyDmxgE105jPxMiyQWM15yp5kHglxbFLoLtGHbwHrBsb dlTvKyUoTjGLimugIqzYn6c13EOQkRo2y37hvyXL/2Pa+0Gu/5f/fkusdvt5Vh4JJf8v XdhA== X-Gm-Message-State: APt69E2HsOhsVkMTTYRyUZ8BOBOaVPGz02gutoFQc36tprQS/ZV8L1e2 SOMW+mqFZXprEz4rgMO/9TEbzQ== X-Received: by 2002:a63:6c05:: with SMTP id h5-v6mr12679444pgc.367.1531136670324; Mon, 09 Jul 2018 04:44:30 -0700 (PDT) Received: from localhost ([103.249.91.93]) by smtp.gmail.com with ESMTPSA id l79-v6sm24741945pfj.179.2018.07.09.04.44.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Jul 2018 04:44:29 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, vivek.gautam@codeaurora.org, andy.gross@linaro.org, Zhang Rui , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 6/7] dt: thermal: tsens: Document the fallback DT property for v2 of TSENS IP Date: Mon, 9 Jul 2018 17:13:28 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We want to create common code for v2 of the TSENS IP block that is used in a large number of Qualcomm SoCs. "qcom,tsens-v2" should be able to handle most of the common functionality start with a common get_temp() function. It is also necessary to split out the memory regions for the TM and SROT register banks because their offsets are not constant across SoC families. Signed-off-by: Amit Kucheria --- .../devicetree/bindings/thermal/qcom-tsens.txt | 25 +++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 06195e8..8f963b1 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -1,10 +1,16 @@ * QCOM SoC Temperature Sensor (TSENS) Required properties: -- compatible : - - "qcom,msm8916-tsens" : For 8916 Family of SoCs - - "qcom,msm8974-tsens" : For 8974 Family of SoCs - - "qcom,msm8996-tsens" : For 8996 Family of SoCs +- compatible: + Must be one of the following: + - "qcom,msm8916-tsens" (MSM8916) + - "qcom,msm8974-tsens" (MSM8974) + - "qcom,msm8996-tsens" (MSM8996) + - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) + - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) + The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with + version 2 of the TSENS IP. MSM8996 is the only exception beacause the generic + property did not exist when support was added. - reg: Address range of the thermal registers - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. @@ -12,7 +18,7 @@ Required properties: - Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify nvmem cells -Example: +Example 1 (legacy support before a fallback tsens-v2 propoerty was introduced): tsens: thermal-sensor@900000 { compatible = "qcom,msm8916-tsens"; reg = <0x4a8000 0x2000>; @@ -20,3 +26,12 @@ tsens: thermal-sensor@900000 { nvmem-cell-names = "caldata", "calsel"; #thermal-sensor-cells = <1>; }; + +Example 2 (for any platform containing v2 of the TSENS IP): +tsens0: tsens@c222000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc263000 0x1ff>, /* TM */ + <0xc222000 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; + };