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[209.132.180.67]) by mx.google.com with ESMTP id a3-v6si552654plc.50.2018.09.12.02.54.16; Wed, 12 Sep 2018 02:54:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VdS5xPkq; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726855AbeILO6C (ORCPT + 13 others); Wed, 12 Sep 2018 10:58:02 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:37579 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726606AbeILO6C (ORCPT ); Wed, 12 Sep 2018 10:58:02 -0400 Received: by mail-ed1-f66.google.com with SMTP id a20-v6so1267004edd.4 for ; Wed, 12 Sep 2018 02:54:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=f5bkI9k4W2c9XfxovD/lpb7m212pStl1rJ1cHBfU/w8=; b=VdS5xPkqWD6huuj6drH9txEG/ptP+bfjajMdOn+cz2qpUtJh5vgHCFhg8v7ObU0t1D OxcIdFHzjrQIscgwb1WYW5ZTRfRNEN0eFsNsLjpJJ2P5KLWhHBfCQyQRjagq5jxRMyMB DQLwd/g2rjIrv71lJ+mmjLQbtv3Z0mHGx+rys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=f5bkI9k4W2c9XfxovD/lpb7m212pStl1rJ1cHBfU/w8=; b=sPjs8aJZs4d9OGaklSpi9vfTlwHO2DwTzS60UXIOruOxBAVl0PO5osCLkaGhTEQiD/ snLrgNHYhOVn+NggIbSWdr23YFrxsEP8O4aH0rs1KinBKhtweKxN38zJMVoKcCuAPaw1 Xh6Ka3Rx5N32OA2CdbQCFzPiSv7JqZT8TkuJAAhd98byXnL46VfKl+f+ViSKMgC8rJ1Z nebRbYwCSqV46EcNHknzscig8jIW1NLc2n46JNtVAWixd1qa5LGDnhGUiRLkf+hW5fPP YpcA4tnDxHi87REzwAct322k55QX4eNiPn5Jjf74C0Fe1onrfsePUCTszm+TDeOl4irK ILSw== X-Gm-Message-State: APzg51DRrmGjWwWPg+EXunlXc5SEjMbT3uqK220+zPI+ofI8KnqP7bnD Idm5Lklh0EQ//5XPDKTorb/zIg== X-Received: by 2002:a50:a804:: with SMTP id j4-v6mr1808568edc.105.1536746054401; Wed, 12 Sep 2018 02:54:14 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id h8-v6sm400574edi.68.2018.09.12.02.54.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:54:13 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 07/16] thermal: tsens: Pass register offsets as private data Date: Wed, 12 Sep 2018 15:22:52 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Registers have moved around across TSENS generations. For example, the CTRL register was at offset 0x0 in the SROT region on msm8916 but is at offset 0x4 in newer v2 based TSENS HW blocks. Allow passing offsets of important registers so that we can continue to use common functions. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-8916.c | 1 + drivers/thermal/qcom/tsens-8974.c | 1 + drivers/thermal/qcom/tsens-v2.c | 2 ++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 9 +++++++++ 5 files changed, 16 insertions(+) -- 2.17.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/thermal/qcom/tsens-8916.c b/drivers/thermal/qcom/tsens-8916.c index c4955c85e922..c6dd620ac029 100644 --- a/drivers/thermal/qcom/tsens-8916.c +++ b/drivers/thermal/qcom/tsens-8916.c @@ -100,5 +100,6 @@ static const struct tsens_ops ops_8916 = { const struct tsens_data data_8916 = { .num_sensors = 5, .ops = &ops_8916, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, .hw_ids = (unsigned int []){0, 1, 2, 4, 5 }, }; diff --git a/drivers/thermal/qcom/tsens-8974.c b/drivers/thermal/qcom/tsens-8974.c index 7e149edbfeb6..3d3fda3d731b 100644 --- a/drivers/thermal/qcom/tsens-8974.c +++ b/drivers/thermal/qcom/tsens-8974.c @@ -232,4 +232,5 @@ static const struct tsens_ops ops_8974 = { const struct tsens_data data_8974 = { .num_sensors = 11, .ops = &ops_8974, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, }; diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 1bdef92e4521..381a212872bf 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -68,10 +68,12 @@ static const struct tsens_ops ops_generic_v2 = { const struct tsens_data data_tsens_v2 = { .ops = &ops_generic_v2, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, }; /* Kept around for backward compatibility with old msm8996.dtsi */ const struct tsens_data data_8996 = { .num_sensors = 13, .ops = &ops_generic_v2, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, }; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 9a8e8f7b4ae1..f1ec9bbe4717 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -144,6 +144,9 @@ static int tsens_probe(struct platform_device *pdev) else tmdev->sensor[i].hw_id = i; } + for (i = 0; i < REG_ARRAY_SIZE; i++) { + tmdev->reg_offsets[i] = data->reg_offsets[i]; + } if (!tmdev->ops || !tmdev->ops->init || !tmdev->ops->get_temp) return -EINVAL; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index b9c4bcf255fa..7b7feee5dc46 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -48,15 +48,23 @@ struct tsens_ops { int (*get_trend)(struct tsens_device *, int, enum thermal_trend *); }; +enum reg_list { + SROT_CTRL_OFFSET, + + REG_ARRAY_SIZE, +}; + /** * struct tsens_data - tsens instance specific data * @num_sensors: Max number of sensors supported by platform * @ops: operations the tsens instance supports * @hw_ids: Subset of sensors ids supported by platform, if not the first n + * @reg_offsets: Register offsets for commonly used registers */ struct tsens_data { const u32 num_sensors; const struct tsens_ops *ops; + const u16 reg_offsets[REG_ARRAY_SIZE]; unsigned int *hw_ids; }; @@ -72,6 +80,7 @@ struct tsens_device { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + u16 reg_offsets[REG_ARRAY_SIZE]; struct tsens_context ctx; const struct tsens_ops *ops; struct tsens_sensor sensor[0];