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From: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
To: Herbert Xu <herbert@gondor.apana.org.au>,
"David S. Miller"
<davem@davemloft.net>,
Rob Herring <robh@kernel.org>,
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CC: <linux-arm-msm@vger.kernel.org>, <linux-crypto@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<quic_yrangana@quicinc.com>
Subject: [PATCH V3 0/2] Enable Inline crypto engine for QCS8300
Date: Mon, 25 Nov 2024 12:27:59 +0530
Message-ID: <20241125065801.1751256-1-quic_yrangana@quicinc.com>
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| Series |
Enable Inline crypto engine for QCS8300
|
expand
|
Document and add device-tree node to enable Inline crypto engine for QCS8300 This series depends on below patch series: https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/ - Reviewed Changes in v3: - Remove "Reviewed-by" tag added incorrectly - Link to v2: https://lore.kernel.org/all/20241122132044.30024-1-quic_yrangana@quicinc.com/ Changes in v2: - extend UFS ICE to the full register range - Link to v1: https://lore.kernel.org/all/20241113043351.2889027-1-quic_yrangana@quicinc.com/ Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> --- Yuvaraj Ranganathan (2): dt-bindings: crypto: ice: document the qcs8300 inline crypto engine arm64: dts: qcom: qcs8300: enable the inline crypto engine .../bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++ 2 files changed, 9 insertions(+)