| Message ID | 20250528144259.2603914-1-john.ernberg@actia.se |
|---|---|
| Headers | show |
| Series | crypto: caam - iMX8QXP support (and related fixes) | expand |
On Wed, May 28, 2025 at 02:43:07PM +0000, John Ernberg wrote: > NXP SoCs like the iMX8QM, iMX8QXP or iMX8DXP use power domains for > resource management. > > Allow specifying them for such SoCs. suggest comment: Add compatible string fsl,imx8qm-caam, and allow power-domains for it. Keep the same restriction for others. > > Signed-off-by: John Ernberg <john.ernberg@actia.se> > > --- > > v3: > - Fix warnings discovered by Rob Herring's bot > - Declare the compatibles correctly (Krzysztof Kozlowski) > > v2: > - Adjust commit message (Frank Li) > - Only allow power-domains when compatible with imx8qm (Frank Li) > --- > .../bindings/crypto/fsl,sec-v4.0.yaml | 45 ++++++++++++++++++- > 1 file changed, 44 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml > index 75afa441e019..a4ada0e2d97c 100644 > --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml > +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml > @@ -46,6 +46,7 @@ properties: > - items: > - enum: > - fsl,imx6ul-caam > + - fsl,imx8qm-caam suggest add fsl,imx8qxp-caam, fsl,imx8dxl-caam also Frank > - fsl,sec-v5.0 > - const: fsl,sec-v4.0 > - const: fsl,sec-v4.0 > @@ -77,6 +78,9 @@ properties: > interrupts: > maxItems: 1 > > + power-domains: > + maxItems: 1 > + > fsl,sec-era: > description: Defines the 'ERA' of the SEC device. > $ref: /schemas/types.yaml#/definitions/uint32 > @@ -106,7 +110,9 @@ patternProperties: > - const: fsl,sec-v5.0-job-ring > - const: fsl,sec-v4.0-job-ring > - items: > - - const: fsl,sec-v5.0-job-ring > + - enum: > + - fsl,imx8qm-job-ring > + - fsl,sec-v5.0-job-ring > - const: fsl,sec-v4.0-job-ring > - const: fsl,sec-v4.0-job-ring > > @@ -116,6 +122,9 @@ patternProperties: > interrupts: > maxItems: 1 > > + power-domains: > + maxItems: 1 > + > fsl,liodn: > description: > Specifies the LIODN to be used in conjunction with the ppid-to-liodn > @@ -212,6 +221,40 @@ required: > - reg > - ranges > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx8qm-caam > + then: > + required: > + - power-domains > + else: > + properties: > + power-domains: false > + > + - if: > + patternProperties: > + '^jr@[0-9a-f]+$': > + type: object > + properties: > + compatible: > + contains: > + const: fsl,imx8qm-job-ring > + then: > + patternProperties: > + '^jr@[0-9a-f]+$': > + type: object > + required: > + - power-domains > + else: > + patternProperties: > + '^jr@[0-9a-f]+$': > + type: object > + properties: > + power-domains: false > + > additionalProperties: false > > examples: > -- > 2.49.0
On Wed, May 28, 2025 at 02:43:08PM +0000, John Ernberg wrote: > From: Horia Geantă <horia.geanta@nxp.com> > > The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and > Assurance Module) like many other iMXs. > > Add the definitions for it. > > Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core > and are not exposed outside it. There's no point to define them in the > bindings as they cannot be used outside the SECO. > > Signed-off-by: Horia Geantă <horia.geanta@nxp.com> > [jernberg: Commit message, fixed dtbs_check warnings, trimmed memory ranges] what's this for? remove it if not related with this patch. Frank > Signed-off-by: John Ernberg <john.ernberg@actia.se> > > --- > > Imported from NXP tree, trimmed down and fixed the dtbs_check warnings. > Constrained the ranges to the needed ones. > Changed the commit message. > Original here: https://github.com/nxp-imx/linux-imx/commit/699e54b386cb9b53def401798d0a4e646105583d > > --- > > v3: > - no changes > > v2: > - Use new compatibles introduced in 3/4 (Frank Li) > --- > .../boot/dts/freescale/imx8-ss-security.dtsi | 38 +++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + > 3 files changed, 40 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi > new file mode 100644 > index 000000000000..9ecabb2d03e9 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi > @@ -0,0 +1,38 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019 NXP > + */ > + > +#include <dt-bindings/firmware/imx/rsrc.h> > + > +security_subsys: bus@31400000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x31400000 0x0 0x31400000 0x90000>; > + > + crypto: crypto@31400000 { > + compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0"; > + reg = <0x31400000 0x90000>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x31400000 0x90000>; > + fsl,sec-era = <9>; > + power-domains = <&pd IMX_SC_R_CAAM_JR2>; > + > + sec_jr2: jr@30000 { > + compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring"; > + reg = <0x30000 0x10000>; > + interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pd IMX_SC_R_CAAM_JR2>; > + }; > + > + sec_jr3: jr@40000 { > + compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring"; > + reg = <0x40000 0x10000>; > + interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pd IMX_SC_R_CAAM_JR3>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > index 6fa31bc9ece8..6df018643f20 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > @@ -612,6 +612,7 @@ vpu_dsp: dsp@556e8000 { > }; > > /* sorted in register address */ > + #include "imx8-ss-security.dtsi" > #include "imx8-ss-cm41.dtsi" > #include "imx8-ss-audio.dtsi" > #include "imx8-ss-vpu.dtsi" > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > index 05138326f0a5..e140155d65c6 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -321,6 +321,7 @@ map0 { > /* sorted in register address */ > #include "imx8-ss-img.dtsi" > #include "imx8-ss-vpu.dtsi" > + #include "imx8-ss-security.dtsi" > #include "imx8-ss-cm40.dtsi" > #include "imx8-ss-gpu0.dtsi" > #include "imx8-ss-adma.dtsi" > -- > 2.49.0
Hi Frank, On Wed, May 28, 2025 at 11:01:33AM -0400, Frank Li wrote: > On Wed, May 28, 2025 at 02:43:08PM +0000, John Ernberg wrote: > > From: Horia Geantă <horia.geanta@nxp.com> > > > > The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and > > Assurance Module) like many other iMXs. > > > > Add the definitions for it. > > > > Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core > > and are not exposed outside it. There's no point to define them in the > > bindings as they cannot be used outside the SECO. > > > > Signed-off-by: Horia Geantă <horia.geanta@nxp.com> > > [jernberg: Commit message, fixed dtbs_check warnings, trimmed memory ranges] > > what's this for? remove it if not related with this patch. These are the adjustments I did to the patch by Horia that I took out of the linux-imx tree (original patch linked below in context). While not part of the process I have seen them used and found them helpful, I can drop it if preferred. Best regards // John Ernberg > > Frank > > > Signed-off-by: John Ernberg <john.ernberg@actia.se> > > > > --- > > > > Imported from NXP tree, trimmed down and fixed the dtbs_check warnings. > > Constrained the ranges to the needed ones. > > Changed the commit message. > > Original here: https://github.com/nxp-imx/linux-imx/commit/699e54b386cb9b53def401798d0a4e646105583d > > > > ---
This series enables the use of the CAAM (Cryptographic Acceleration and Assurance Module) on the iMX8QXP (and its variants). v3: (detailed changelog in each patch) - Fix devicetree CI detected errors (Rob Herring's bot) - Declare the compatibles correctly in bindings (Krzysztof Kozlowski) v2: https://lore.kernel.org/linux-crypto/20250527071552.1424997-1-john.ernberg@actia.se/T - Clarify in the commit message how the crash fix works (Frank Li) - Restrict power-domains only for iMX8Q* SoCs in bindings (Frank Li) - Collect tags v1: https://lore.kernel.org/linux-crypto/20250523131814.1047662-1-john.ernberg@actia.se/T Horia Geantă (1): arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support John Ernberg (3): crypto: caam - Prevent crash on suspend with iMX8QM / iMX8ULP crypto: caam - Support iMX8QXP and variants thereof dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP .../bindings/crypto/fsl,sec-v4.0.yaml | 45 ++++++++++++++++++- .../boot/dts/freescale/imx8-ss-security.dtsi | 38 ++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + drivers/crypto/caam/ctrl.c | 7 +-- drivers/crypto/caam/intern.h | 1 + 6 files changed, 89 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi